User guide

Chapter 7: Custom PHY IP Core 7–7
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 7–6 provides more information about the word alignment function.
Rate Match FIFO
The rate match FIFO compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
(SKP) symbols or ordered-sets from the inter-packet gap (IPG) or idle streams. It
deletes SKP symbols or ordered-sets when the upstream transmitter reference clock
frequency is greater than the local receiver reference clock frequency. It inserts SKP
symbols or ordered-sets when the local receiver reference clock frequency is greater
than the upstream transmitter reference clock frequency.
If you enable the rate match FIFO, the parameter editor provides options to enter the
rate match insertion and deletion patterns. The lower 10 bits are the control pattern,
and the upper 10 bits are the skip pattern. Table 7–7 lists the settings available on the
Rate Match tab.
Table 7–6. Word Aligner Options
Configuration
PMA-PCS
Interface
Width (bits)
Word
Alignment
Mode
Word
Alignment
Pattern
Length (bits)
Word Alignment Behavior
Custom
single
deserializer
width
8
Manual
alignment
16
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
10
Manual
alignment
7, 10
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
Automatic
synchronized
state machine
Data must be 8B/10B encoded and aligns to selected
word aligner pattern.
Custom
double
deserializer
width
16
Manual
alignment
8, 16, 32
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
20
Manual
alignment
8, 16, 32
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
Automatic
Synchronized
Stat
e Machine
7 and 10 bits
Automatically selected word aligner pattern length and
pattern.
Table 7–7. Rate Match FIFO Options (Part 1 of 2)
Name Value Description
Enable rate match FIFO On/Off
Turn this option on, to enable the rate match functionality. Turning
this option on adds the
rx_rmfifodatainserted , and
rx_rmfifodatadeleted status signals to your PHY.
Rate match
insertion/deletion +ve
disparity pattern
1101000011
1010000011
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.