User guide

8–10 Chapter 8: Low Latency PHY IP Core
Parameter Settings
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
XCVR_RX_LINEAR_EQUALIZER_
CONTROL
Receiver Linear Equalizer
Control
Static control for the continuous time
equalizer in the receiver buffer. The
equalizer has 16 distinct settings from
0 –15 corresponding to the increasing
AC gain.
1 –16 Pin
Analog Parameter with Computed Default Value
XCVR_RX_COMMON_MODE_
VOLTAGE
Receiver Buffer Common
Mode Voltage
Receiver buffer common-mode
voltage.
VTT_0P80V
VTT_0P75V
VTT_0P70V
VTT_0P65V
VTT_0P60V
VTT_0P55V
VTT_0P50V
VTT_0P35V
VTT_PUP
_WEAK
VTT_PDN
WEAK
TRISTATE1
VTT_PDN_
STRONG
VTT_PUP_
STRONG
TRISTATE2
TRISTATE3
TRISTATE4
Pin
XCVR_RX_ENABLE_LINEAR_
EQUALIZER_PCIEMODE
Receiver Linear Equalizer
Control (PCI Express)
If enabled equalizer gain control is
driven by the PCS block for PCI
Express. If disabled equalizer gain
control is determined by the
XCVR_RX_LINEAR_EQUALIZER_SETT
ING
assignment.
TRUE
FALSE
Pin
XCVR_RX_EQ_BW_SEL
Receiver Equalizer Gain
Bandwidth Select
Sets the gain peaking frequency for the
equalizer. For data-rates of less than
6.5Gbps set to HALF. For higher data-
rates set to FULL.
FULL
HALF
Pin
XCVR_RX_SD_ENABLE
Receiver Signal Detection
Unit Enable/Disable
Enables or disables the receiver signal
detection unit.
TRUE
FALSE
Pin
XCVR_RX_SD_OFF
Receiver Cycle Count
Before Signal Detect Block
Declares Loss Of Signal
Number of parallel cycles to wait
before the signal detect block declares
loss of signal.
0–29
Pin
XCVR_RX_SD_ON
Receiver Cycle Count Before
Signal Detect Block Declares
Presence Of Signal
Number of parallel cycles to wait
before the signal detect block declares
presence of signal.
0–16
Pin
XCVR_RX_SD_THRESHOLD
Receiver Signal Detection
Voltage Threshold
Specifies signal detection voltage
threshold level.
0 –7
Pin
Table 8–8. Transceiver and PLL Assignments for Stratix V Devices (Sheet 1 of 3)
QSF Assignment Name
Pin Planner and
Assignment Editor
Name
Description Options Assign To