User guide

Chapter 8: Low Latency PHY IP Core 8–13
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
f For more information about _hw.tcl files refer to refer to the Component Interface Tcl
Reference chapter in volume 1 of the Quartus II Handbook.
The following sections describe each interface.
Avalon-ST TX and RX Data Interface to the FPGA Fabric
Table 8–9 describes the signals in the Avalon-ST interface. These signals are named
from the point of view of the MAC so that the TX interface is an Avalon-ST sink
interface and the RX interface is an Avalon-ST source.
Serial Data Interface
Table 8–10 describes the signals that comprise the serial data interface.
Table 8–9. Avalon-ST interface
Signal Name Direction Description
tx_parallel_data[<n><w>-1:0] Sink
This is TX parallel data driven from the MAC FPGA fabric. The ready
latency on this interface is 0, so that the PCS in Low-Latency
Bypass Mode or the MAC in PMA Direct mode must be able to
accept data as soon as it comes out of reset.
tx_clkout[<n>-1:0] Output This is the clock for TX parallel data.
tx_ready[<n>-1:0] Output
When asserted, indicates that the Low Latency IP core has exited
the reset state is ready to receive data from the MAC. This signal is
available if you select Enable embedded reset control on the
Additional Options tab.
rx_parallel_data[ < n > <w>-1:0] Source
This is RX parallel data driven by the Low Latency PHY IP core.
Data driven from this interface is always valid.
rx_clkout[<n>-1:0] Output Low speed clock recovered from the serial data.
rx_ready[<n>-1:0] Output
This is the ready signal for the RX interface. The ready latency on
this interface is 0, so that the MAC must be able to accept data as
soon as the PMA comes out of reset. This signal is available if you
select Enable embedded reset control on the Additional Options
tab.
Table 8–10. Serial Data Interface
Signal Name Direction Description
rx_serial_data[<n>-1:0] Sink Differential high speed input serial data.
tx_serial_data [<n>-1:0] Source Differential high speed output serial data.