User guide

9–2 Chapter 9: Deterministic Latency PHY IP Core
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
and status registers. This is a standard, memory-mapped protocol that is normally
used to read and write registers and memory. The transceiver reconfiguration
interface connects to the Altera Transceiver Reconfiguration Controller IP core which
can dynamically reconfigure transceiver settings. Finally, the PMA transmits and
receives serial data which connects to an optical link.
f For more information about the Avalon-ST and Avalon-MM protocols, refer to the
Avalon Interface Specifications.
Auto-Negotiation
The Deterministic Latency PHY IP core supports auto-negotiation. When
auto-negotiation is required, the channels initialize at the highest supported
frequency and switch to successively lower data rates if frame synchronization is not
achieved. If your design requires auto-negotiation, choose a base data rate that
minimizes the number of PLLs required to generate the clocks required for data
transmission. By selecting an appropriate base data rate, you can change data rates by
changing the divider used by the clock generation block. Table 9–1 shows an example
where setting two base data rates, 9830.4 and 6144 Mbps, with the appropriate clock
dividers generates almost the full range of data rates required by the CPRI protocol.
Table 9–1. Recommended Base Data Rate and Clock Divisors for CPRI
Data Rate (Mbps) Base Data Rate (Mbps) Clock Divider
614.4 4915.2 8
1228.8 4915.2 4
2457.6 4915.2 2
3072.0 6144.0 2
4915.2 4915.2 1
6144.0 6144.0 1