User guide

Chapter 9: Deterministic Latency PHY IP Core 9–5
Device Family Support
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 9–3 shows the total latency through the RX PCS in parallel clock cycles. The RX
compensation FIFO is in register mode.
Table 9–4 shows the total latency through the TX and RX PMA in UI.
1 There is a small discrepancy between simulation of the delays through the PMA
serializer and deserializer and hardware modeling of these delays.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 9–5 shows the level of support offered by the Deterministic Latency PHY IP core
for Altera device families.
Double word with byte serializer 1.0 0.5 0.5 0 2.0
Double word without byte serializer 1.0 1.0 2.0 0 3.0
Table 9–2. TX PCS Total Latency
Datapath Attributes
TX Phase
Comp FIFO
Serializer 8B/10B Bitslip
Total Clock
Cycles
Table 9–3. RX PCS Total Latency
Datapath Attributes
RX Phase
Comp FIFO
Byte
Ordering
Deserializer 8B/10B
Word
Aligner
Total Clock
Cycles
Single word with byte deserializer 1.0 1.0 1.5 0.5 2.0 6.0
Single word without byte deserializer 1.0 1.0 1.0 1.0 4.0 8.0
Double word with byte deserializer 1.0 1.0 1.5 0.5 2.5 6.5
Double word without byte deserializer 1.0 1.0 1.0 1.0 5.0 9.0
Table 9–4. PMA Datapath Total Latency
(1)
Device
TX PMA Latency in UI RX PMA Latency in UI
Single Width
with 10 bits
Double Width
with 20 bits
Single Width
with 10 bits
Double Width
with 20 bits
Arria V 13 23 54 84
Stratix V 23 43 53 83
Note to Table 9–4:
(1) The numbers in this table are from simulation.
Table 9–5. Device Family Support
Device Family Support
Arria V devices Preliminary
Stratix V devices Preliminary
Other device families No support