User guide

Chapter 9: Deterministic Latency PHY IP Core 9–7
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 9–7 lists the available channel widths available at selected frequencies. The
channel width options are restricted by the following maximum FPGA-PCS fabric
interface frequencies:
■ Arria V devices—159.375 MHz
■ Stratix V devices—221 MHz when the byte serializer and deserializer are disabled
■ Stratix V devices —325 MHz when the byte serializer and deserializer are enabled
Base data rate
1 × Data rate
2 × Data rate
4 × Data rate
8 × Data rate
For systems that transmit and receive data at more than one data
rate, select a base data rate that minimizes the number of PLLs
required to generate the clocks for data transmission. Table 9–1 on
page 9–2 lists the recommended Base data rates for various Data
rates.
The available options are dynamically computed based on the Data
rate you specified as long as those Base data rates are within the
frequency range of the PLL.
Input clock frequency
Data rate/20
Data rate/10
Data rate/8
Data rate/5
Data rate/4
Data rate/2.5
Data rate/2
Data rate/1.25
Data rate/1
This is the reference clock for the PHY PLL. The available options are
based on the Base data rate specified.
Table 9–6. General Options (Part 2 of 2)
Name Value Description
Table 9–7. Sample Channel WIdth Options for Supported Serial Data Rates
Serial Data Rate (Mbps)
Channel Width (FPGA-PCS Fabric)
Single-Width Double-Width
8-Bit 16-Bit 16-Bit 32-Bit
614.4 vv——
1228.8 vvvv
2457.6 — vvv
3072 — v v v
4915.2 — — — v
6144 — — — v