User guide

9–8 Chapter 9: Deterministic Latency PHY IP Core
Parameter Settings
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Additional Options
Table 9–8 lists the settings available on the Additional Options tab.
Table 9–8. Additional Options (Part 1 of 2)
Name Value Description
Word alignment mode
Deterministic
latency state
machine
The word aligner restores word boundaries of received data based on
a predefined alignment pattern. The word aligner automatically
performs an initial alignment to the specified word pattern after reset
deassertion.
You can select 1 of the following 2 modes:
■ Deterministic latency state machine–In this mode, the RX word
aligner automatically searches for the word alignment pattern after
reset completes. After the word aligner detects the specified word
alignment pattern, it sends
RX_CLKSLIP to the RX PMA
deserializer indicating the number of bits to slip to compensate for
the bits that were slipped to achieve word alignment. When
RX_CLKSLIP has a non-zero value, the deserializer either skips one
serial bit or pauses the serial clock for one cycle. As a result, the
period of the parallel clock could be extended by 1 unit interval (UI)
during the clock slip operation. This procedure avoids using the TX
bit slipper to ensure constant round-trip delay. In this mode, the
specified word alignment pattern, which is currently forced to
K28.5 (0011111010) is always placed in the least significant byte
(LSB) of a word with a fixed latency of 3 cycles. User logic can
assume the LSB placement. Altera recommends the deterministic
latency state machine mode for new designs.
During the word alignment process, the parallel clock shifts the
phase to align to the data. This phase shifting will be 2/10 cycles
(20%) in 10 bit mode, 2/20 cycles (10%) in 20 bit mode, and 2/40
cycles (5%) in 40 bit mode.
For double-width datapaths using deterministic latency state
machine mode, after the initial alignment following the deassertion
of reset, the Avalon-MM register big
rx_enapatternalign (not
available as a signal) must be reasserted to initiate another pattern
alignment. Asserting
rx_enapatternalign , may cause the extra
shifting in the RX datapath if
rx_enablepatternalign is
asserted while bit slipping is in progress; consequently
rx_enapatternalign should only be asserted under the
following conditions:
■ rx_syncstatus is asserted
■ rx_bitslipboundaryselectout changes from a non-zero
value to zero or 1
Manual
■ Manual–In this mode, the RX word aligner parses the incoming
data stream for a specific alignment character. Once it identifies
this pattern, it shifts the input stream to align the data and also
outputs the number of bits slipped on
bitslipboundaryselectot[4:0] for latency compensation on
the TX datapath. This mode is provided for backwards
compatibility with designs implemented in Stratix IV and Arria II
devices.