User guide

Chapter 9: Deterministic Latency PHY IP Core 9–9
Parameter Settings
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Analog Options
You specify the analog parameters for Stratix V devices using the Quartus II
Assignment Editor, the Pin Planner, or through the Quartus II Settings File (.qsf). The
default values for analog options fall into three categories:
■ Global— These parameters have default values that are independent of other
parameter settings.
■ Computed—These parameters have an initial default value that is recomputed
based on other parameter settings.
■ Proxy—These parameters have default values that are place holders. The
Quartus II software selects these initial default values based on your design;
however, Altera recommends that you replace these defaults with values that
match your electrical board specification.
TX bitslip On/Off
TX bitslip is enabled whenever the word aligner is in Manual
alignment mode. The TX bitslipper uses the value of
bitslipboundarselect[4:0] to compensate for bits slipped on
the RX datapath to achieve deterministic latency.
Enable run length violation
checking
On/Off
If you turn this option on, you can specify the run length which is the
maximum legal number of contiguous 0s or 1s. This option also
creates the
rx_rlv output signal which is asserted when a run length
violation is detected.
Run length 5–160
Specifies the threshold for a run-length violation. Must be a multiple
of 5.
Create optional word aligner
status ports
On/Off
Enable this option to include the
rx_patterndetect and
rx_syncstatus ports.
Create optional 8B/10B
control and status ports
On/Off
Enable this option to include the 8B/10B
rx_runningdisp ,
rx_errdetect , and rx_disperr signals at the top level of the
Deterministic Latency PHY IP core.
Create PMA optional status
ports
On/Off
Enable this option to include the 8B/10B
rx_is_lockedtoref ,
rx_is_lockedtodata , and rx_signaldetect signals at the top
level of the Deterministic Latency PHY IP core.
Avalon data interfaces On/Off
This option is typically required if you are planning to import your
Deterministic Latency PHY IP core into a Qsys system.
Enable embedded reset
controller
On/Off
When you turn this option On, the embedded reset controller handles
reset of the TX and RX channels at power up. If you turn this option
Off, you must design a reset controller that manages the following
reset signals:
tx_digitalreset , tx_analogreset , tx_cal_busy ,
rx_digitalreset , rx_analogreset , and rx_cal_busy .
Table 9–8. Additional Options (Part 2 of 2)
Name Value Description