User guide

Chapter 10: Transceiver Reconfiguration Controller 10–3
System Overview
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
System Overview
Figure 10–1 illustrates the Transceiver Reconfiguration Controller’s role in a Stratix V
design.
As Figure 10–1 illustrates, an embedded controller programs the Transceiver
Reconfiguration Controller using its Avalon-MM slave interface. The
reconfig_to_xcvr and reconfig_from_xcvr buses include the Avalon-MM address ,
read , write, readdata , writedata , and signals that connect to features related to
calibration and signal integrity.
The Transceiver Reconfiguration Controller provides two modes to dynamically
reconfigure transceiver settings:
■ Register Based—In this access mode you can directly reconfigure a transceiver
PHY IP core using the Transceiver Reconfiguration Controller’s reconfiguration
management interface. You initiate reconfiguration using a series of Avalon-MM
reads and writes to the appropriate registers of the Transceiver Reconfiguration
Controller. The Transceiver Reconfiguration Controller translates the device
independent commands received on the reconfiguration management interface to
device dependent commands on the transceiver reconfiguration interface. For
more information, refer to “Channel and PLL Reconfiguration” on page 10–21.
Figure 10–1. Transceiver Reconfiguration Controller
Note to Figure10–1:
(1) You can locate the embedded controller on-chip or on the PCB.
to and from
Embedded
Controller
TX and RX
Serial Data
Avalon-MM master interface
Transceiver
Reconfiguration
Controller
S
M
Avalon-MM slave interface
S
reconfig_to_xcvr[<n>:0]
reconfig_mif_address[31:0]
reconfig_mif_read
Reconfiguration
Management
Interface
reconfig_mif_readdata[15:0]
reconfig_mif_waitrequest
Streaming Data
reconfig_from_xcvr[<n>:0]
Transceiver PHY
Registers to
reconfigure
User Application
Including MAC
Stratix V GX, GS, or GT Device
.
.
.
.
.
.
(Note 1)
S
M
Master
M
S
MIF
ROM