User guide
10–4 Chapter 10: Transceiver Reconfiguration Controller
Device Family Support
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
1 For more information about Avalon-MM interfaces including timing 
diagrams, refer to the Avalon Interface Specifications.
■ Streamer Based —This access mode allows you to either stream a MIF that 
contains the reconfiguration data or perform direct writes to perform 
reconfiguration. The streaming mode uses a memory initialization file (.mif) to 
stream an update to the transceiver PHY IP core. The .mif file can contain changes 
for many settings. For example, a single .mif file might contain changes to the PCS 
datapath settings, clock settings, and PLL parameters. You specify the .mif using 
write commands on the Avalon-MM PHY management interface. After the 
streaming operation is specified, the update proceeds in a single step. For more 
information, refer to “Streamer Based Reconfiguration” on page 10–28. In the 
direct write mode, you perform Avalon-MM reads and writes to initiate a 
reconfiguration of the PHY IP. For more information, refer to “Direct Write 
Reconfiguration” on page 10–29.
Table 10–1 shows the features that you can reconfigure or control using register-based 
and MIF-based access modes.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families. 
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 10–2 lists the level of support offered by the Transceiver Reconfiguration 
Controller for Altera device families.
Table 10–1. Reconfiguration Feature Access Modes
Feature Register-Based Streamer-Based
PMA settings, including V
OD
, pre-emphasis, RX 
equalization DC gain, RX equalization control 
vv
Pre-CDR and post-CDR loopback modes v —
AEQ mode v —
Eye Monitor v —
ATX Tuning v —
Reference clock — v
TX PLL clock switching  vv
Channel interface — v
Channel internals — v
Table 10–2. Device Family Support
Device Family Support
Stratix V devices Preliminary
Other device families No support 










