User guide

10–6 Chapter 10: Transceiver Reconfiguration Controller
Parameter Settings
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 10–4 lists the available options.
Table 10–4. General Options
Name Value Description
Device family
Arria V
Stratix V
This IP core is available for Arria V and Stratix V devices. It is not
functional for Arria V devices. It is available to establish the correct
connections between the transceiver PHY and Transceiver
Reconfiguration Controller.
Interface Bundles
Number of reconfiguration
interfaces
<IF>
Specifies the total number of reconfiguration interfaces that
connect to the Transceiver Reconfiguration Controller. There is
one interface for each channel and TX PLL.
When you specify the parameters for a transceiver PHY, The
message window displays the number of interfaces required.
Optional interface grouping
<Grp
1
>,<Grp
2
>,
<Grp
3
>
Specifies the grouping of reconfiguration interfaces as a
comma-separated list with each integer indicating the total
number of reconfiguration interfaces that are connected to a
transceiver PHY instance. Leave this entry blank if all
reconfiguration interfaces connect to the same transceiver PHY
instance.
Refer to “Understanding Logical Channel Numbering” on
page 10–31 for more information about grouping interfaces.
Transceiver Calibration Functions
Enable offset cancellation On
When enabled, the Transceiver Reconfiguration Controller
includes the offset cancellation functionality. This option is always
on. Offset cancellation occurs automatically at power-up and runs
only once.
Enable duty cycle calibration On/Off
When enabled, this circuitry improves the duty cycle of the
transceiver PHY IP core transmitters.
Enable auxiliary transmit (ATX)
PLL calibration
On/Off
When enabled, an algorithm that improves the signal integrity of
the ATX PLL is included in the Transceiver Reconfiguration
Controller IP core.
Analog Features
Enable Analog controls On/Off
When enabled, RX and RX signal conditioning features are
enabled.
Enable EyeQ block On/Off
When enabled, you can use the EyeQ, the on-chip signal quality
monitoring circuitry, to estimate the actual eye opening at the
receiver.
Enable adaptive equalization
(AEQ) block
On/Off
When enabled, the Transceiver Reconfiguration Controller
includes logic to perform AEQ.
Reconfiguration Features
Enable channel/PLL
reconfiguration
On/Off
When enabled, the Transceiver Reconfiguration Controller
includes logic to include both channel and PLL reconfiguration.
Enable PLL reconfiguration
support block
On/Off
When enabled, the Transceiver Reconfiguration Controller
includes logic to perform PLL reconfiguration.