User guide

10–8 Chapter 10: Transceiver Reconfiguration Controller
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Transceiver Reconfiguration Interface
Table 10–6 describes the signals that comprise the dynamic reconfiguration interface.
The Transceiver Reconfiguration Controller communicates with the PHY IP cores
using this interface.
Reconfiguration Interface Management Interface
The reconfiguration management interface is an Avalon-MM slave interface. You can
use an embedded controller to drive this interface. Alternatively, you can use a finite
state machine to control all Avalon-MM reads and writes to the Transceiver
Reconfiguration Controller. This interface provides access to the Transceiver
Reconfiguration Controller’s Avalon-MM registers.
f For more information about the Avalon-MM protocol, including timing diagrams,
refer to the Avalon Interface Specifications. Table 10–7 list the signals in reconfiguration
management interface.
Table 10–6. Transceiver Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr[(<n>×70)-1:0]
(1)
Output
Parallel reconfiguration bus from the Transceiver
Reconfiguration Controller to the PHY IP core.
reconfig_from_xcvr[(<n>×46)-1:0]
(1)
Input
Parallel reconfiguration bus from the PHY IP core to the
Transceiver Reconfiguration Controller.
reconfig_busy Output
When asserted, indicates that a reconfiguration operation is in
progress and no further reconfiguration operations should be
performed. You can monitor this signal to determine the
status of the Transceiver Reconfiguration Controller.
Alternatively, you can monitor the
busy bit of the control
and
status registers of any reconfiguration feature to
determine the status of the Transceiver Reconfiguration
Controller.
Note to Table 10–6:
(1) <n> is the number of reconfiguration interfaces connected to the Transceiver Reconfiguration Controller.
Table 10–7. Reconfiguration Management Interface
Signal Name Direction Description
mgmt_clk_clk Input
Avalon-MM clock input. The frequency range for the
mgmt_clk_clk is 100–125 MHz.
mgmt_rst_reset Input
This signal resets the Transceiver Reconfiguration Controller. This
signal is active high and level sensitive.
reconfig_mgmt_address[6:0] Input 7-bit Avalon-MM address.
reconfig_mgmt_writedata[31:0] Input Input data.
reconfig_mgmt_readdata[31:0] Output Output data.
reconfig_mgmt_write Input Write signal. Active high.
reconfig_mgmt_read Input Read signal. Active high.