User guide

Chapter 10: Transceiver Reconfiguration Controller 10–13
EyeQ
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
EyeQ uses a phase interpolator and sampler to estimate the vertical and horizontal
eye opening using the values that you specify for the
horizontal phase and vertical
height
. (Refer to Table 10–12 on page 10–14.) The phase interpolator generates a
sampling clock and the sampler examines the data from the receiver output. The
sampled data is deserialized and sent to the IP core where the PRBS checker
determines the BER. As the phase interpolator output clock phase is shifted by small
increments, the data error rate goes from high to low to high if the receiver is good.
The number of steps of valid data is defined as the width of the eye. If none of the
steps yields valid data, the width of the eye is equal to 0, which means the eye is
closed.
Table 10–11 lists the memory-mapped EyeQ registers that you can access using
Avalon-MM reads and writes on reconfiguration management interface.
1 All undefined register bits are reserved.
Table 10–11. Eye Monitor Registers
Recon
-fig
Addr
Bits R/W Register Name Description
7’h10 [9:0] RW
logical channel number
The logical channel number. Must be specified when
performing dynamic updates. The Transceiver
Reconfiguration Controller maps the logical address to the
physical address.
7’h12
[9] R
control and status
Error
. When asserted, indicates an invalid channel or
address.
[8] R
Busy . When asserted, indicates that a reconfiguration
operation is in progress.
[1] W
Read . Writing a 1 to this bit triggers a read operation.
[0] W
Write . Writing a 1 to this bit triggers a write operation.
7’h13 [5:0] RW
eyeq offset Specifies the 6-bit offset of the EyeQ register.
7’h14 [15:0] RW
data Reconfiguration data for the transceiver PHY registers.