User guide

10–24 Chapter 10: Transceiver Reconfiguration Controller
Streamer Module
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 10–23 lists the internal Streamer Module registers that you access to control and
determine the status of a MIF operation.
1 All undefined register bits are reserved and must be set to 0.
The following sections describe operations in Streamer modes 0 and 1.
Mode 0 Streaming a MIF for Reconfiguration
In mode 0, you can stream the contents of a MIF containing the reconfiguration data
to the transceiver PHY IP core instance. You specify this mode by writing a value of
2'b00 into bits 2 and 3 of the
control and status register, as indicated in Table 10–22
on page 10–23. Mode 0 simplifies the reconfiguration process because all
reconfiguration data is stored in the MIF, which is streamed to the transceiver PHY IP
in a single step.
The MIF can change PLL settings, reference clock inputs, or the TX PLL selection.
After the MIF streaming update is complete, all transceiver PHY IP core settings
reflect the value specified by the MIF. Refer to “Streamer Based Reconfiguration” on
page 10–28 for an example of a MIF update.
Table 10–23. Streamer Module Internal MIF Register Offsets
Offset
Bits R/W
Register Name Description
0x0 [31:0] RW
MIF base address Specifies the MIF base address.
0x1 [2] RW
Clear error status
Writing a 1 to this bit clears any error currently
recorded in an indirect register. This register self
clears.
Any error detected in the error registers prevents
MIF streaming. If an error occurs, you must clear
the error register before restarting the Streamer.
[0] RW
Start MIF stream
Writing a 1 to this register, triggers a MIF
streaming operation. This register self clears.
0x2
[4] RO
MIF or Channel
mismatch
When asserted, indicates the MIF type specified is
incorrect. For example, the logical channel is
duplex, but the MIF type specifies an RX only
channel. The following 4 MIF types are defined:
■ Duplex
■ TX PLL (CMU)
■ RX only channel
■ TX only channel
[2] RO
PLL
reconfiguration IP
error
When asserted, indicates that an error occurred
changing a refclk or clock generation block
setting.
[1] RO
MIF opcode error
When asserted, indicates that an undefined
opcode ID was specified in the .mif file, or the
first entry in the .mif file was not a start of MIF
opcode.
[0] RO
Invalid register
access
When asserted, indicates that the offset register
address specified is out of range.