User guide

Chapter 10: Transceiver Reconfiguration Controller 10–27
Procedures for Reconfiguration
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Procedures for Reconfiguration
As Table 10–1 indicates, some features can only be reconfigured using register-based
accesses, some features can only be reconfigured using MIF-based accesses, and some
features can be reconfigured using either access mode. The following sections discuss
both modes.
Changing Transceiver Settings Using Register-Based Reconfiguration
In register-based mode, you use a sequence of Avalon-MM writes and reads to update
individual transceiver settings. The following section describes how to perform a
register-based reconfiguration read and write.
Register-Based Write
Complete the following steps to perform a register-based write:
1. Read the
control and status register busy bit (bit 8) until it is clear.
2. Write the logical channel number of the channel to be updated to the
logical
channel number register.
3. Write the <feature> offset address.
4. Write the appropriate data value to the
data register.
5. Write the
control and status register write bit to 1’b1.
6. Read the
control and status register busy bit. Continue to read the busy bit while
its value is one.
7. When
busy = 0, the Transceiver Reconfiguration Controller has updated the logical
channel specified in Step 2 with the data specified in Step 3.
Example 10–2 shows a reconfiguration that changes the logical channel o V
OD
setting
to 40.
Register-Based Read
Complete the following steps for a read:
1. Read the
control and status register busy bit (bit 8) until it is clear.
2. Write the logical channel number of the channel to be read to the
logical channel
number register.
3. Write the <feature> offset address.
Example 10–2. Register-Based Write of Logical Channel 0 V
OD
Setting
#Setting logical channel 0
write_32 0x8 0x0
#Setting offset to VOD
write_32 0xB 0x0
#Setting data register to 40
write_32 0xC 0x28
#Writing all data
write_32 0xA 0x1