User guide

10–28 Chapter 10: Transceiver Reconfiguration Controller
Procedures for Reconfiguration
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
4. Write the control and status register read bit to 1’b1.
5. Read the
control and status register busy bit. Continue to read the busy until the
value is zero.
6. Read the
data register to get the data.
Example 10–3 illustrates a read of the pre-emphasis pretap value for logical channel 2.
Changing Transceiver Settings Using Streamer-Based Reconfiguration
The Streamer’s registers allow you to change to the PCS datapath settings, clock
settings, and PLL parameters by reading the new settings from an on- or off-chip
ROM. “Streamer Module Registers” on page 10–23 lists the Streamer’s
memory-mapped registers that you can access using Avalon-MM read and write
commands on reconfiguration management interface.
The following sections show how to change transceiver settings using Streamer
modes 0 and 1.
Streamer Based Reconfiguration
Follow these steps to reconfigure a transceiver setting by streaming the contents of a
MIF file through the Streamer Module.
1. Write the logical channel number to the Streamer
logical channel register.
2. Write MIF mode, 2’b00, to the Streamer
control and status register mode bits.
3. Write the MIF base address, 0x0, to the Streamer
offset register.
4. Write the base address of the MIF file to the Streamer
data register.
5. Write the Streamer
control and status register write bit to 1'b1 to initiate a write
of all the data set in in the previous steps.
6. Write to the Streamer internal
offset register with the value to start a MIF stream,
0x1.
7. Write the Streamer internal
data register with the value 0x1 to setup the streaming
of the MIF.
8. Write to the Streamer
control and status register to 1'b1, to initiate the streaming
operation.
9. Read the
control and status register busy bit. When the busy bit is deasserted, the
MIF streaming operation has completed.
Example 10–3. Register-Based Read of Logical Channel 2 Pre-Emphasis Pretap Setting
#Setting logical channel 2
write_32 0x8 0x2
#Setting offset to pre-emphasis pretap
write_32 0xB 0x1
#Writing the logical channel and offset for pre-emphasis pretap
write_32 0xA 0x1
#Reading data register for the pre-emphasis pretap value
read_32 0xC