User guide

Chapter 10: Transceiver Reconfiguration Controller 10–37
Reconfiguration Controller to PHY IP Connectivity
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Reconfiguration Controller to PHY IP Connectivity
You can connect a single Transceiver Reconfiguration Controller to all of the
transceiver channels and PLLs in your design. You can also use multiple Transceiver
Reconfiguration Controllers to facilitate placement and routing of the FPGA.
However, the three, upper or lower contiguous channels in a transceiver bank must be
connected to the same reconfiguration controller.
Figure 10–11 illustrates connections between the Transceiver Reconfiguration
Controller and transceiver channels after Quartus II compilation.
Figure 10–12 illustrates incorrect connections between two Transceiver
Reconfiguration Controllers and six transceiver channels. Two Transceiver
Reconfiguration Controllers cannot access a single reconfiguration interface because
there is no arbitration logic to prevent concurrent access. The configuration shown in
Figure 10–12 results in a Quartus II compilation error.
Figure 10–11. Correct Connections
Figure 10–12. Incorrect Connections
Transceiver
Reconfiguration
Controller
Transceiver Bank
3 Transceiver
Channels
3 Transceiver
Channels
10 GBASE-R
(unused)
(unused)
Custom
Custom
CMU PLL
S
to Embedded
Processor
Reconfig to
and from
Transceiver
Stratix V GX, GS, or GT Device
3 Transceiver
Channels
Transceiver Bank
3 Transceiver
Channels
Not Allowed
Custom
10 GBASE-R
10 GBASE-R
Custom
Custom
CMU PLL
Transceiver
Reconfiguration
Controller
S
to Embedded
Processor
Transceiver
Reconfiguration
Controller
S
to Embedded
Processor
Reconfig to
and from
Transceiver
Stratix V GX, GS, or GT Device