User guide

11–2 Chapter 11: Migrating from Stratix IV to Stratix V Devices
Dynamic Reconfiguration of Transceivers
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
This chapter enumerates the differences between the ALTGX megafunction for use
with Stratix IV GX devices and the protocol-specific transceiver PHYs for use with
Stratix V GX devices in the current release. It includes the following topics:
■ Dynamic Reconfiguration of Transceivers
■ XAUI PHY
■ PHY IP Core for PCI Express PHY (PIPE)
■ Custom PHY
Dynamic Reconfiguration of Transceivers
This section covers dynamic reconfiguration of transceivers in Stratix V and Stratix IV
devices. Dynamic reconfiguration interface is completely new in Stratix V devices.
You cannot automatically migrate a dynamic reconfiguration solution from Stratix IV
to Stratix V devices.
Dynamic Reconfiguration for Stratix V Transceivers
Stratix V devices that include transceivers must use the Altera Transceiver
Reconfiguration Controller that contains the offset cancellation logic to compensate
for variations due to PVT. Initially, each transceiver channel and each TX PLL has its
own parallel, dynamic reconfiguration bus, named
reconfig_from_xcvr[45:0] and
reconfig_to_xcvr[69:0]
. The reconfiguration bus includes Avalon-MM signals to
read and write registers and memory and test bus signals. When you instantiate a
transceiver PHY in a Stratix V device, the transceiver PHY IP core provides
informational messages specifying the number of required reconfiguration interfaces
in the message pane as Example 11–1 illustrates.
Although you must initially create a separate reconfiguration interface for each
channel and TX PLL in your design, when the Quartus II software compiles your
design, it reduces the number of reconfiguration interfaces by merging
reconfigurations interfaces. The synthesized design typically includes a
reconfiguration interface for three channels. Allowing the Quartus II software to
merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver
channels.
Dynamic Reconfiguration for Stratix IV Transceivers
Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP core
to implement dynamic reconfiguration. The ALTGX_RECONFIG IP core always
includes the following two serial buses:
■ reconfig_from[<n>16:0] — this bus connects to all the channels in a single quad.
<n> is the number of quads connected to the ALTGX_RECONFIG IP core.
Example 11–1. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 5 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver channels.
Reconfiguration interface offset 4 is connected to the transmit PLL.