User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Revision History
The table below displays the revision history for the chapters in this user guide.
Date Version Changes Made SPR
Custom
March 2012 1.6
■ Added register definitions for address range 0x080–0x085. .
Low Latency PHY
March 2012 1.6
■ Removed register definitions for address range 0x080–0x085. .
10GBASE-R
February 2012 1.5
■ Added datapath latency numbers for Stratix V devices.
■ Corrected bit range for ERRORED_BLOCK_COUNT .
■ Added statement that the the cal_blk_powerdown (0x021) and pma_tx_pll_is_locked
(0x022) registers are only available when the Use external PMA control and reconfig option
is turned On on the Additional Options tab of the GUI.
■ Clarified that the BER count functionality is for Stratix IV devices only.
■ Removed pma_rx_signaldetect register. The 10GBASE-R PHY does not support this
functionality.
XAUI
February 2012 1.5
■ Removed reset bits at register 0x081. The reset implemented Cat register 0x044 provides
more comprehensive functionality.
■ Removed pma_rx_signaldetect register. The XAUI PHY does not support this
functionality.
PCI Express (PIPE)
February 2012 1.5
■ Updated definition of fixedclk . It can be derived from pll_ref_clk .
Custom
February 2012 1.5
■ Removed register definitions for Low Latency PHY.
Low Latency PHY
February 2012 1.5
■ Added register definitions for Low Latency PHY.
Deterministic Latency PHY
February 2012 1.5
■ Removed pma_rx_signaldetect register. The Deterministic Latency PHY does not
support this functionality.
■ Updated the definition of deterministic latency word alignment mode to include the fact that
the word alignment pattern, which is currently forced to K28.5 = 0011111010 is always
placed in the least significant byte (LSB) of a word with a fixed latency of 3 cycles.