User guide

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Revision History
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
May 2011 1.2
■ Added support for DDR XAUI
■ Added support for Arria II GZ and HardCopy IV
■ Added example testbench
■ Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_xcvr and
reconfig_to_xcvr , respectively.
■ Updated definitions of rx_digital_reset and tx_digital_reset for the soft XAUI
implementation in Table 4–17 on page 4–19.
■ Changed description of rx_syncstatus register and signals to specify 2 bits per channel in
hard XAUI and 1 bit per channel in soft XAUI implementations.
■ Corrected bit sequencing for 0x084, 0x085 and 0x088 in Table 4–17 on page 4–19, as
follows:
■ patterndetect = 0x084, bits [15:8]
■ syncstatus = 0x084, bits [7:0]
■ errordetect = 0x085, bits [15:8]
■ disperr = 0x085, bits [7:0]
■ rmfifofull = 0x088, bits [7:4]
■ rmfifoempty = 0x088, bits [3:0]
Interlaken PHY Transceiver
May 2011 1.2
■ Added details about the 0 ready latency for tx_ready .
■ Added PLL support to lane rate parameter description in Table 5–2 on page 5–2.
■ Moved dynamic reconfiguration for the transceiver outside of the Interlaken PHY IP Core.
The reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Added a reference to PHY IP Design Flow with Interlaken for Stratix V Devices which is a
reference design that implements the Interlaken protocol in a Stratix V device.
■ Changed supported metaframe lengths from 1–8191 to 5–8191.
■ Added pll_locked output port.
■ Added indirect_addr register at 0x080 for use in accessing PCS control and status
registers.
■ Added new Bonded group size parameter.
PHY IP Core for PCI Express PHY (PIPE)
May 2011 1.2
■ Renamed to PHY IP Core for PCI Express.
■ Moved dynamic reconfiguration for the transceiver outside of the PHY IP Core. The
reconfiguration signals now connect to a separate Reconfiguration Controller IP Core.
■ Removed ×2 support.
Date Version Changes Made SPR