User guide

Additional InformationAdditional Information Info–9
Revision History
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Interlaken PHY Transceiver
December
2010
1.1
■ Added simulation support in ModelSim SE, Synopsys VCS MX, Cadence NCSim
■ Changed number of lanes supported from 4–24 to 1–24.
■ Changed reference clock to be 1/20th rather than 1/10th the lane rate.
■ Renamed management interface, adding phy_ prefix
■ Changed phy_mgmt_address from 16 to 9 bits.
■ Changed many signal names, refer to Figure 5–2 on page 5–8.Changed register map to
show word addresses instead of a byte offset from a base address.
PCI Express PHY (PIPE)
December
2010
1.1
■ Added simulation support in ModelSim SE
■ Added PIPE low latency configuration option
■ Changed phy_mgmt_address from 16 to 9 bits.
■ Changed register map to show word addresses instead of a byte offset from a base address.
■ Added tx_ready , rx_ready , pipe_txswing , and pipe_rxeleciidle signals
■ Added rx_errdetect , rx_disperr , and rx_a1a2sizeout register fields
Custom PHY Transceiver
December
2010
1.1
■ Added support for 8B/10B encoding and decoding in Stratix V devices
■ Added support for rate matching in Stratix V devices.
■ Added support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices
■ Renamed management interface, adding phy_ prefix
■ Changed phy_mgmt_address from 8 to 9 bits.
■ Added many optional status ports and renamed some signals. Refer to Figure 7–2 on
page 7–16 and subsequent signal descriptions.
■ Changed register map to show word addresses instead of a byte offset from a base address.
Low Latency PHY IP Core
December
2010
1.1
■ Renamed management interface, adding phy_ prefix
■ Changed phy_mgmt_address from 16 to 9 bits.
■ Changed register map to show word addresses instead of a byte offset from a base address.
■ Removed rx_offset_cancellation_done signal. Internal reset logic determines when
offset cancellation has completed.
■ Removed support for Stratix IV GX devices.
Transceiver Reconfiguration Controller
December
2010
1.1
■ Reconfiguration is now integrated into the XAUI PHY IP core and 10GBASE-R PHY IP core.
■ Revised register map to show word addresses instead of a byte offset from a base address.
Migrating from Stratix IV to Stratix V
December
2010
1.1
■ Changed phy_mgmt_address from 16 to 9 bits.
Date Version Changes Made SPR