User guide

Chapter 3: 10GBASE-R PHY IP Core 3–11
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
h For more information about the Pin Planner, refer to About the Pin Planner in
Quartus II Help. For more information about the Assignment Editor, refer to About
the Assignment Editor in Quartus II Help.
f For more information about Quartus II Settings, refer to Quartus II Settings File
Manual.
Interfaces
This section describes interfaces of the 10GBASE-R PHY IP Core. It includes the
following topics:
■ Ports
■ Register Interface
■ Dynamic Reconfiguration
Ports
Figure 3–3 illustrates the top-level signals of the 10BASE-R PHY.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the Hardware Component Description File (_hw.tcl). If you turn on Show signals, the
block diagram displays all top-level signal names.
f For more information about _hw.tcl files refer to refer to the Component Interface Tcl
Reference chapter in volume 1 of the Quartus II Handbook.
The following sections describe the signals in each interface.
Figure 3–3. 10GBASE-R PHY Top-Level Signals
f
xgmii_tx_dc <n> [71:0]
tx_ready
xgmii_tx_clk
xgmii_rx_dc
<n> [71:0]
rx_ready
rx_data_ready[
<n> -1:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
10GBASE-R Top-Level Signals
Clock
Signals for
External PMA and
Reconfiguration
Stratix IV Devices
Reconfiguration
Stratix V Devices
rx_serial_data <n>
tx_serial_data <n>
gxb_pdn
pll_locked
pll_pdn
cal_blk_pdn
rx_recovered_clk[
<n> ]
reconfig_to_xcvr[3:0]
reconfig_from_xcvr[
<n> /4)17-1:0]
reconfig_to_xcvr[(
<n> 70-1):0]
reconfig_from_xcvr[(
<n> 46-1):0]
rx_block_lock
rx_hi_ber
pll_ref_clk
Transceiver
Serial Data
SDR XGMII Tx
Inputs from MAC
SDR XGMII Rx
Outputs from PCS
towards MAC
Avalon-MM PHY
Management
Interface
Status