User guide

3–18 Chapter 3: 10GBASE-R PHY IP Core

Interfaces

Altera Transceiver PHY IP Core March 2012 Altera Corporation

User Guide

Table 3–17 specifies the registers that you can access over the Avalon-MM PHY

management interface using word addresses and a 32-bit embedded processor. A

single address space provides access to all registers.

1 Writing to reserved or undefined register addresses may have undefined side effects.

Table 3–17. 10GBASE-R Register Descriptions (Part 1 of 3)

Word

Addr

Bit R/W Name Description

PMA Common Control and Status - working in 12.0.

0x021 [31:0] RW

cal_blk_powerdown

Writing a 1 to channel <n> powers down the calibration

block for channel <n> . This register is only available if you

select Use external PMA control and reconfig on the

Additional Options tab of the GUI.

0x022 [31:0] RO

pma_tx_pll_is_locked

Bit[P] indicates that the TX clock multiplier unit CMU PLL

[P] is locked to the input reference clock. This register is

only available if you select Use external PMA control and

reconfig on the Additional Options tab of the GUI.

Reset Control Registers–Automatic Reset Controller

0x041 [31:0] RW

reset_ch_bitmask

Reset controller channel bitmask for digital resets. The

default value is all 1 s. Channel <n> can be reset when

bit<n> = 1. Channel <n> cannot be reset when bit<n>=0.

0x042 [1:0]

reset_control

(write)

Writing a 1 to bit 0 initiates a TX digital reset using the reset

controller module. The reset affects channels enabled in the

reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX

digital reset of channels enabled in the

reset_ch_bitmask. Both bits 0 and 1 self-clear.

reset_status

(read)

Reading bit 0 returns the status of the reset controller TX

ready bit. Reading bit 1 returns the status of the reset

controller RX ready bit.