User guide

3–20 Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Dynamic Reconfiguration
This section includes information about dynamic reconfiguration of the transceivers
in Stratix IV and Stratix V devices.
Dynamic Reconfiguration for Stratix IV Devices
Table 3–18 describes the additional top-level signals 10GBASE-R PHY IP core when
the configuration includes external modules for PMA control and reconfiguration.
You enable this configuration by turning on Use external PMA control and reconfig
available for Stratix IV GT devices. This configuration is illustrated in Figure 3–2 on
page 3–2.
0x082
[0] R
PCS_STATUS
For Stratix IV devices, when asserted indicates that the PCS
link is up. This bit is only available for Stratix IV devices.
[1] R
HI_BER
When asserted by the BER monitor block, indicates that the
PCS is recording a high BER. This bit is only for Stratix IV
devices.
From block: BER monitor
[2] R
BLOCK_LOCK
When asserted by the block synchronizer, indicates that the
PCS is locked to received blocks.
From Block: Block synchronizer
[3] R
TX_FIFO_FULL
When asserted, indicates the TX FIFO is full.
From block: TX FIFO
[4] R
RX_FIFO_FULL
When asserted, indicates the RX FIFO is full.
From block: RX FIFO
[5] R
RX_SYNC_HEAD_ERROR
For Stratix V devices, when asserted, indicates an RX
synchronization error. This signal is Stratix V devices only.
[6] R
RX_SCRAMBLER_ERROR
For Stratix V devices, when asserted, indicates an RX
scrambler error. This signal is Stratix V devices only.
[7] R
RX_DATA_READY
When asserted indicates that the RX interface is ready to
send out received data.
From block: 10 Gbps Receiver PCS
0x083
[5:0] R
BER_COUNT[5:0]
For Stratix IV devices only, records the bit error rate (BER).
From block: BER monitor
[13:6] R
ERROR_BLOCK_COUNT[7:0]
For Stratix IV devices only, records the number of blocks
that contain errors.
From Block: Block synchronizer
Table 3–17. 10GBASE-R Register Descriptions (Part 3 of 3)
Word
Addr
Bit R/W Name Description
Table 3–18. External PMA and Reconfiguration Signals (Part 1 of 2)
Signal Name Direction Description
gxb_pdn
Input When asserted, powers down the entire GX block. Active high.
pll_locked
Output When asserted, indicates that the PLL is locked. Active high.
pll_pdn
Input When asserted, powers down the TX PLL. Active high.