User guide

Chapter 3: 10GBASE-R PHY IP Core 3–21
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 3–19 describes the signals in the reconfiguration interface. This interface uses
the Avalon-MM PHY Management interface clock.
Dynamic Reconfiguration for Stratix V Devices
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
For Stratix V devices, each channel and each TX PLL have separate dynamic
reconfiguration interfaces. The parameter editor provides informational messages on
the connectivity of these interfaces. Example 3–1 shows the messages for a single
duplex channel.
cal_blk_pdn
Input When asserted, powers down the calibration block. Active high.
cal_blk_clk
Input
Calibration clock. For Stratix IV devices only. It must be in the range
37.5–50 MHz. You can use the same clock for the phy_mgmt_clk and
the
cal_blk_clk .
rx_recovered_clk[<n>:0]
Output This is the RX clock, which is recovered from the received data stream.
reconfig_to_xcvr[3:0]
Input
Reconfiguration signals from the Transceiver Reconfiguration Controller
to the PHY device. This signal is only available in Stratix IV devices.
reconfig_from_xcvr
[(<n>/4)17-1:0]
Output
Reconfiguration RAM. The PHY device drives this RAM data to the
transceiver reconfiguration IP. This signal is only available in Stratix IV
devices.
Table 3–18. External PMA and Reconfiguration Signals (Part 2 of 2)
Signal Name Direction Description
Table 3–19. Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(<n>70-1):0] Sink
Reconfiguration signals from the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces. This signal is only available in
Stratix V devices.
reconfig_from_xcvr [(<n>46-1):0] Source
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces. This signal is only available in
Stratix V devices.