User guide

3–22 Chapter 3: 10GBASE-R PHY IP Core
TimeQuest Timing Constraints
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Although you must initially create a separate reconfiguration interface for each
channel and TX PLL in your design, when the Quartus II software compiles your
design, it reduces the number of reconfiguration interfaces by merging
reconfiguration interfaces. The synthesized design typically includes a
reconfiguration interface for three channels. Allowing the Quartus II software to
merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver
channels. For more information about transceiver reconfiguration refer to Chapter 10,
Transceiver Reconfiguration Controller.
TimeQuest Timing Constraints
The timing constraints for Stratix IV GX designs are in alt_10gbaser_phy.sdc. If your
design does not meet timing with these constraints, use LogicLock
TM
for the
alt_10gbaser_pcs block. You can also apply LogicLock to the alt_10gbaser_pcs and
slightly expand the lock region to meet timing.
h For more information about LogicLock, refer to About LogicLock Regions in Quartus II
Help.
1 For Stratix V devices, timing constraints are built into the HDL code.
Example 3–2 provides the Synopsys Design Constraints File (.sdc) timing constraints
for the 10GBASE-R IP core. To pass timing analysis, you must decouple the clocks in
different time domains. Be sure to verify the each clock domain is correctly buffered in
the top level of your design. You can find the .sdc file in your top-level working
directory. This is the same directory that includes your top-level .v or .vhd file.
Example 3–1. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 2 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offset 0 is connected to the transceiver channel.
Reconfiguration interface offset 1 is connected to the transmit PLL.
Example 3–2. Synopsys Design Constraints for Clocks
#**************************************************************
# Timing Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clocks
#**************************************************************
create_clock -name {xgmii_tx_clk} -period 6.400 -waveform { 0.000 3.200 } [get_ports
{xgmii_tx_clk}]
create_clock -name {phy_mgmt_clk} -period 20.00 -waveform { 0.000 10.000 } [get_ports
{phy_mgmt_clk}]
create_clock -name {pll_ref_clk} -period 1.552 -waveform { 0.000 0.776 } [get_ports
{ref_clk}]
#derive_pll_clocks
derive_pll_clocks -create_base_clocks
#derive_clocks -period "1.0"