User guide

Chapter 4: XAUI PHY IP Core 4–23
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
This section includes information about the dynamic reconfiguration interface. The
Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX use the
ALTGX_RECONFIG Megafunction for transceiver reconfiguration. The Stratix V
device uses the Transceiver Reconfiguration Controller IP core for dynamic
reconfiguration. For more information about this IP core, refer to Chapter 10,
Transceiver Reconfiguration Controller.
f For more information about the ALTGX_RECONFIG Megafunction, refer to
ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices in volume 2 of the
Stratix IV Device Handbook.
Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and
Stratix IV GX Devices
Table 4–18 describes the signals in the reconfiguration interface. If your XAUI PHY IP
core includes a single transceiver quad, these signals are internal to the core. If your
design uses more than one quad, the reconfiguration signals are external.
0x089
[31:3] — Reserved —
[2:0]
R,
sticky
phase_comp_fifo_error[2:
0]
Indicates a TX phase compensation FIFO overflow or
underrun condition on the corresponding lane. Reading the
value of the
phase_comp_fifo_error register clears the
bits.This register is only available in the hard XAUI
implementation
From block: TX phase compensation FIFO.
0x08a [0] RW
simulation_flag
Setting this bit to 1 shortens the duration of reset and loss
timer when simulating. Altera recommends that you keep
this bit set during simulation.
Table 4–17. XAUI PHY IP Core Registers (Part 5 of 5)
Word
Addr
Bits R/W Register Name Description
Table 4–18. Dynamic Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr[3:0] Input
Reconfiguration signals from the Transceiver Reconfiguration IP
core to the XAUI transceiver.
reconfig_from_xcvr[<n>:0] Output
Reconfiguration signals from the XAUI transceiver to the
Transceiver Reconfiguration IP core. The size of this bus is
depends on the device. For the soft PCS in Stratix IV GX and GT
devices,
<n> = 68 bits. For hard XAUI variants, <n> = 16. For
Stratix V devices, the number of bits depends on the number of
channels specified. Refer to Chapter 10, Transceiver
Reconfiguration Controller for more information.