User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
5. Interlaken PHY IP Core
Interlaken is a high speed serial communication protocol for chip-to-chip packet
transfers. The Altera Interlaken PHY IP core implements Interlaken Protocol
Specification, Rev 1.2. It supports multiple instances, each with 1 to 24 lanes running at
up to 10.3125 Gbps on Stratix V devices. The key advantages of Interlaken are
scalability and its low I/O count compared to earlier protocols such as SPI 4.2. Other
key features include flow control, low overhead framing, and extensive integrity
checking. The Interlaken physical coding sublayer (PCS) transmits and receives
Avalon-ST data on its FPGA fabric interface. It transmits and receives high speed
differential serial data using the PCML I/O standard. Figure 5–1 illustrates the
top-level modules of the Interlaken PHY.
f For more information about the Avalon-ST protocol, including timing diagrams, refer
to the Avalon Interface Specifications.
Interlaken operates on 64-bit data words and 3 control bits, which are striped round
robin across the lanes to reduce latency. Striping renders the interface independent of
exact lane count. The protocol accepts packets on 256 logical channels and is
expandable to accommodate up to 65,536 logical channels. Packets are split into small
bursts which can optionally be interleaved. The burst semantics include integrity
checking and per channel flow control.
The Interlaken PCS supports the following framing functions on a per lane basis:
■ Gearbox
■ Block synchronization
■ Metaframe generation and synchronization
■ 64b/67b encoding and decoding
■ Scrambling and descrambling
Figure 5–1. Interlaken PHY IP Core
PCS PMA
Serializer
De-
Serializer
and CDR
HSSI I/O
HSSI I/O
Interlaken PHY IP Core
FPGA
Fabric
tx_serial_data
Avalon-ST TX
Avalon-ST RX
rx_serial_data
up to
10.3125 Gbps
Metaframe Generation
CRC32 Generation
Scrambler
Disparity Generation
TX Gearbox
TX Datapath
RX Gearbox
Block Synchronizer
Disparity Checker
Descrambler
Metaframe Synchronizer
CRC32 Checker
RX Datapath