User guide

Chapter 5: Interlaken PHY IP Core 5–11
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
rx_parallel_data<n>[66] Source
This is an active-high synchronous status signal indicating that block
lock (frame synchronization) and frame lock (metaframe boundary
delineation) have been achieved. The Interlaken MAC should use this
signal to indicate that Metaframe synchronization has been achieved
for this lane.
If the RX PCS FIFO reaches the empty state or is in an empty state,
rx_parallel_data<n>[66] Block Lock and Frame Lock status
signals are deasserted in the next clock cycle.
rx_parallel_data<n>[70] indicating metaframe lock and
rx_parallel_data<n>[69] indicating that the first Interlaken
synchronization word alignment pattern has been received remain
asserted.
rx_parallel_data<n>[67] Source When asserted, indicates an RX FIFO overflow error.
rx_parallel_data<n>[68] Source
When asserted, indicates that the RX FIFO is partially empty and is
still accepting data from the frame synchronizer. This signal is
asserted when the RX FIFO has limited data. The Interlaken MAC
should begin reading from the RX FIFO when this signal is
deasserted, indicating sufficient FIFO contents to prevent underflow.
The MAC should continue to read the RX FIFO to prevent overflow as
long as this signal is not reasserted.
rx_parallel_data<n>[69] Source
When asserted, indicates that the RX FIFO has found the first
Interlaken synchronization word alignment pattern. For very short
metaframes, this signal may be asserted after the frame synchronizer
state machine validates frame synchronization and asserts
rx_parallel_data<n>[70] because this signal is asserted by the
RX FIFO which is the last PCS block in the RX datapath.
This signal is optional. If the RX PCS FIFO reaches the empty state or
is in an empty state,
rx_parallel_data<n>[70] indicating
metaframe lock and
rx_parallel_data<n>[69] indicating that the
first Interlaken synchronization word alignment pattern has been
received remain asserted, but
rx_parallel_data<n>[66] block
lock and frame lock status signal are deasserted in the next clock
cycle.
rx_parallel_data<n>[70] Source
When asserted, indicates that the RX frame synchronization state
machine has found and received 4 consecutive, valid synchronization
words. The frame synchronization state machine requires 4
consecutive synchronization words to exit the presync state and
enter the synchronized state.
This signal is optional. If the RX PCS FIFO reaches an empty state or
is in an empty state,
rx_parallel_data<n>[70] indicating
metaframe lock and
rx_parallel_data<n>[69] indicating that the
first Interlaken synchronization word alignment pattern has been
received remain asserted but
rx_parallel_data<n>[66] block
lock and frame lock status signal are deasserted in the next clock
cycle.
rx_parallel_data<n>[71] Source
When asserted, indicates a CRC32 error in this lane. This signal is
optional.
rx_ready Source
When asserted, indicates that the RX interface has exited the reset
state and is ready for service. The Interlaken MAC must wait for
rx_ready to be asserted before initiating data transfer on any lanes.
Table 5–7. Avalon-ST RX Signals (Part 2 of 3)
Signal Name Direction Description