User guide
5–12 Chapter 5: Interlaken PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
PLL Interface
Table 5–9 describes the signals in the PLL interface.
TX and RX Serial Interface
Table 5–9 describes the signals in the chip-to-chip serial interface.
Optional Clocks for Deskew
Table 5–10 describes the optional clocks that you can create to reduce clock skew.
rx_clkout
Output
Output clock from the RX PCS. The frequency of this clock equals the
Lane rate divided by 40, which is the PMA serialization factor.
rx_fifo_clr<n>
Input
When asserted, the RX FIFO is flushed. This signal allows you to
clear the FIFO if synchronization is not achieved.
rx_dataout_bp<n>
Sink
When asserted, enables reading of data from the RX FIFO. This signal
functions as a read enable. The RX interface has a ready latency of 1
cycle so that
rx_paralleldata
<n>
[63:0]
and
rx_paralleldata<n>[65]
are valid the cycle after
rx_dataout_bp
<n> is asserted.
rx_user_clkout
Output
Master channel
rx_user_clkout
is available when you do not
create the optional
rx_coreclkin
.
Table 5–7. Avalon-ST RX Signals (Part 3 of 3)
Signal Name Direction Description
Table 5–8. Serial Interface
Signal Name Direction Description
pll_ref_clk
Input
Reference clock for the PHY PLLs. Refer to the Lane rate entry in
Table 5–2 on page 5–2 for required frequencies.
Table 5–9. Serial Interface
Signal Name Direction Description
tx_serial_data
Output
Differential high speed serial output data using the PCML I/O
standard. Clock is embedded in the serial data stream.
rx_serial_data
Input
Differential high speed serial input data using the PCML I/O standard.
Clock is recovered from the serial data stream.
Table 5–10. Serial Interface
Signal Name Direction Description
tx_coreclkin
Input
When enabled
tx_coreclkin
is available as input port which drives
the write side of TX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled,
tx_cllkout
drives the write side
the TX FIFO.
tx_clkout
must be used when the number of lanes is
greater than 1.
rx_coreclkin
Input
When enabled,
rx_coreclkin
is available as input port which drives
the read side of RX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled,
rx_user_clkout,
which is the
master
rx_clkout
for all the bonded receiver lanes, is internally
routed to drive the read side the RX FIFO.