User guide

Chapter 5: Interlaken PHY IP Core 5–15
Interfaces
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Transceiver Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature (PVT). These process
variations result in analog voltages that can be offset from required ranges. The
calibration performed by the dynamic reconfiguration interface compensates for
variations due to PVT.
For Stratix V devices, each channel and each TX PLL have separate dynamics
reconfiguration interfaces. The parameter editor provides informational messages on
the connectivity of these interfaces. Example 5–1 shows the messages for a 4-channel
Interlaken PHY IP core.
Although you must initially create a separate reconfiguration interface for each
channel and TX PLL in your design, when the Quartus II software compiles your
design, it reduces the number of reconfiguration interfaces by merging
reconfiguration interfaces. The synthesized design typically includes a
reconfiguration interface for three channels. Allowing the Quartus II software to
merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver
channels. For more information about transceiver reconfiguration refer to Chapter 10,
Transceiver Reconfiguration Controller.
Stratix V Device Registers
[27] R
rx_crc32_err
Asserted by the CRC32 checker to indicate a CRC error in
the corresponding RX lane.
From block: CRC32 checker.
0x081 [25] R
rx_sync_lock
Asserted by the frame synchronizer to indicate that 4 frame
synchronization words have been received so that the RX
lane is synchronized.
From block: Frame synchronizer.
[24] R
rx_word_lock
Asserted when the first alignment pattern is found. The RX
FIFO generates this synchronous signal.
From block: The RX FIFO generates this synchronous
signal.
Table 5–12. Interlaken PHY Registers (Part 3 of 3)
Word
Addr
Bits R/W Register Name Description
Example 5–1. Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 5 reconfiguration interfaces for connection to the external
reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver channels.
Reconfiguration interface offset 4 is connected to the transmit PLL.