User guide

5–16 Chapter 5: Interlaken PHY IP Core
TimeQuest Timing Constraints
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Table 5–13 describes the signals in the reconfiguration interface. This interface uses
the Avalon-MM PHY Management interface clock.
TimeQuest Timing Constraints
You must add the following TimeQuest constraint to your Synopsys Design
Constraints File (.sdc) timing constraint file:
derive_pll_clocks -create_base_clocks
Simulation Files and Example Testbench
Refer to “Running a Simulation Testbench” on page 1–4 for a description of the
directories and files that the Quartus II software creates automatically when you
generate your Interlaken PHY IP core.
f Refer to the Altera wiki for an example testbench that you can use as a starting point
in creating your own verification environment.
Table 5–13. Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(<n>70)-1:0] Sink
Reconfiguration signals from the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces. <n> initially includes the total
number transceiver channels and TX PLLs before
optimization/merging.
reconfig_from_xcvr [(<n>46)-1:0] Source
Reconfiguration signals to the Transceiver Reconfiguration
Controller. <n> grows linearly with the number of
reconfiguration interfaces.
<n> initially includes the total
number transceiver channels before optimization/merging.