User guide

March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
6. PHY IP Core for PCI Express (PIPE)
The Altera PHY IP core for PCI Express (PIPE) implements physical coding sublayer
(PCS) and physical media attachment (PMA) modules as defined by the Intel PHY
Interface for PCI Express (PIPE) Architecture specification. The PHY IP core for PCI
Express connects to a PHYMAC for PCI Express to create a complete design. Altera
supports the Gen1 and Gen2 specifications and ×1, ×4, or ×8 operation for a total
aggregate bandwidth of 2 to 32 Gbps.
Figure 6–1 illustrates the top-level blocks of the PCI Express PHY (PIPE) for
Stratix V GX devices.
f For more detailed information about the PCI Express PHY PIPE transceiver channel
datapath, clocking, and channel placement, refer to the “PCI Express” section in the
Transceiver Protocol Configurations in Stratix V Devices chapter of the Stratix V Device
Handbook.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 6–1 shows the level of support offered by the PCI Express PIPE IP core for
Altera device families
Figure 6–1. PCI Express PHY (PIPE) with Hard IP PCS and PMA in Stratix V GX Devices
PHY IP Core for PCI Express
Avalon-ST Tx and Rx
to ASIC,
ASSP,
FPGA
from
PCI Express
MACPHY
Stratix V FPGA
PCS:
8B/10B
Elastic Buffer
Rx Detection
PMA:
Analog Buffers
SERDES
10-bit Interface
Avalon-MM Cntrl and Status
Avalon-ST PIPE
Avalon-ST Reconfig
HSSI
Differential PCML
Table 6–1. Device Family Support
Device Family Support
Stratix V devices–Hard PCS + PMA Preliminary
Other device families No support