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Arria 10 Transceiver PHY User Guide

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UG-01143

2015.05.11

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Summary of content (626 pages)

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Arria 10 Transceiver PHY User Guide Subscribe Send Feedback UG-01143 2015.05.11 101 Innovation Drive San Jose, CA 95134 www.altera.
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TOC-2 Arria 10 Transceiver PHY Overview Contents Arria 10 Transceiver PHY Overview ..................................................................1-1 Device Transceiver Layout......................................................................................................................... 1-3 Arria 10 GX Device Transceiver Layout.......................................................................................1-3 Arria 10 GT Device Transceiver Layout.........................................
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Arria 10 Transceiver PHY Overview TOC-3 IP Core File Locations................................................................................................................... 2-75 Interlaken.................................................................................................................................................... 2-76 Metaframe Format and Framing Layer Control Word............................................................ 2-78 Interlaken Configuration Clocking and Bonding.....
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TOC-4 Arria 10 Transceiver PHY Overview Receiver Input Pins........................................................................................................................3-29 PLL Cascading as an Input Reference Clock Source.................................................................3-30 Reference Clock Network............................................................................................................. 3-30 Global Clock or Core Clock as an Input Reference Clock................
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Arria 10 Transceiver PHY Overview TOC-5 Transmitter Datapath....................................................................................................................5-19 Receiver Datapath.......................................................................................................................... 5-29 Arria 10 Standard PCS Architecture....................................................................................................... 5-37 Transmitter Datapath.....................
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TOC-6 Arria 10 Transceiver PHY Overview Transceiver Channel Calibration Registers..................................................................................7-3 Fractional PLL Calibration Registers............................................................................................ 7-4 ATX PLL Calibration Registers......................................................................................................7-4 Capability Registers.......................................................
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1 Arria 10 Transceiver PHY Overview 2015.05.11 UG-01143 Subscribe Send Feedback This user guide provides details about the Arria® 10 transceiver physical (PHY) layer architecture, PLLs, clock networks and transceiver PHY IP. It also provides protocol specific implementation details and describes features such as reset controller, and dynamic reconfiguration.
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1-2 UG-01143 2015.05.11 Arria 10 Transceiver PHY Overview Standard Power Mode (1), (2), (3) Device Variant Chip-to-Chip Reduced Power Mode (1), (2), (3) Backplane Chip-to-Chip GX( 611 Mbps to 17.4 Gbps 611 Mbps to 16.0 Gbps 611 Mbps to 11.3 Gbps 611 Mbps to 10.3125 Gbps GT (5)611 Mbps to 17.4 Gbps 611 Mbps to 17.4 Gbps 611 Mbps to 11.3 Gbps 611 Mbps to 10.
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UG-01143 2015.05.11 Arria 10 GX Device Transceiver Layout 1-5 Figure 1-3: Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard IP Blocks.
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1-8 UG-01143 2015.05.11 Arria 10 GX Device Transceiver Layout Figure 1-6: Arria 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block CH5 CH4 CH3 CH2 CH1 CH0 GXBL1D Transceiver Bank GXBL1C Transceiver Bank Transceiver Bank PCIe Gen1 - Gen3 Hard IP (with CvP) GX 048 EF29 GX 032 EF29 GX 027 EF29 GX 032 EF27 GX 027 EF27 GX 022 EF29 GX 022 EF27 GX 016 EF29 GX 016 EF27 Note: (1) These devices have transceivers only on the left hand side of the device.
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UG-01143 2015.05.11 1-9 Arria 10 GT Device Transceiver Layout Arria 10 GT Device Transceiver Layout The largest GT device has 96 transceiver channels and four PCI Express Hard IP blocks. All GT devices have a total of 16 GT transceiver channels that can support data rates up to 28.3 Gbps. In GT devices, transceiver banks GXBL1E, GXBL1F, GXBL1G, and GXBL1H each contain four GT transceiver channels. Channels 0,1,3, and 4 can be used as GT or GX transceiver channels.
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1-10 UG-01143 2015.05.11 Arria 10 GT Device Transceiver Layout Note: Refer to Arria 10 GT Channel Usage on page 2-313 for details on Arria 10 GT channel usage restrictions.
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UG-01143 2015.05.11 Arria 10 GT Device Transceiver Layout 1-11 Figure 1-10: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks GT Channels Capable of Short Reach 28.
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1-12 UG-01143 2015.05.11 Arria 10 GX and GT Device Package Details In GT devices that have transceivers on both sides of the device, the GX transceiver channels on the right side can be used in reduced power mode. In GT devices where none of the GT channels are used, the transceiver channels can be used as GX channels in standard or reduced power mode.
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UG-01143 2015.05.11 Arria 10 SX Device Transceiver Layout 1-13 Table 1-4: Package Details for GX and GT Devices with Transceivers and Hard IP Blocks Located on the Left and Right Side Periphery of the Device • Package F40: 40 mm x 40 mm package size; 1517 pins. • Package F45: 45mm x 45mm package size; 1932 pins.
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UG-01143 2015.05.11 Arria 10 SX Device Transceiver Layout 1-15 Figure 1-12: Arria 10 SX Device with 12 Transceiver Channels and One Hard IP Block CH5 CH4 CH3 CH2 CH1 CH0 GXBL1D Transceiver Bank GXBL1C Transceiver Bank Transceiver Bank PCIe Gen1 - Gen3 Hard IP (with CvP) SX 048 EF29 SX 032 EF29 SX 032 EF27 SX 027 EF29 SX 027 EF27 SX 022 EF29 SX 022 EF27 SX 016 EF29 SX 016 EF27 Note: (1) These devices have transceivers only on the left hand side of the device.
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1-16 UG-01143 2015.05.11 Arria 10 SX Device Package Details Related Information • • • • Arria 10 Avalon-ST Interface for PCIe Datasheet Arria 10 Avalon-MM Interface for PCIe Datasheet Arria 10 Avalon-MM DMA Interface for PCIe Datasheet Arria 10 Avalon-ST Interface with SR-IOV for PCIe Datasheet Arria 10 SX Device Package Details The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for Arria 10 SX devices.
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UG-01143 2015.05.11 Transceiver Bank Architecture 1-17 Each transceiver bank includes six transceiver channels in all devices except for the devices with 66 transceiver channels. These devices (with 66 transceiver channels) have both six channel and three channel transceiver banks. The uppermost transceiver bank on the left and the right side of these devices is a three channel transceiver bank. All other devices contain only six channel transceiver banks.
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UG-01143 2015.05.11 Transceiver Bank Architecture 1-19 Figure 1-16: GT Transceiver Bank Architecture In GT devices, the transceiver banks GXBL1E, GXBL1F, GXBL1G, and GXBL1H include GT channels.
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1-20 UG-01143 2015.05.11 PHY Layer Transceiver Components Related Information • PLLs and Clock Networks on page 3-1 • Transceiver Basics Online training course for transceivers. PHY Layer Transceiver Components Transceivers in Arria 10 devices support both Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer. A PMA is the transceiver's electrical interface to the physical medium.
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UG-01143 2015.05.11 The GT Transceiver Channel 1-21 Table 1-6: PCS Types Supported by GX Transceiver Channels PCS Type Data Rate Standard PCS 611 Mbps to 12 Gbps Enhanced PCS 960 Mbps (12) to 17.4 Gbps PCIe Gen3 PCS 8 Gbps Note: 1. The GX channel can also operate in PCS Direct configuration for data rates from 611 Mbps to 17.4 Gbps. 2. The transmitter minimum operational data rate is 611 Mbps. For transmitter data rates less than 611 Mbps, oversampling must be applied at the transmitter. 3.
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1-22 UG-01143 2015.05.11 The GT Transceiver Channel Figure 1-18: GT Transceiver Channel in Full Duplex Mode Operating Between 17.4 Gbps and 28.
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UG-01143 2015.05.11 Transceiver Phase-Locked Loops 1-23 Note: 1. The GT channels can also operate in PCS Direct configuration for data rates from 611 Mbps to 28.3 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration used to support GT data rates from 17.4 Gbps to 28.3 Gbps. 2. The transmitter minimum operational data rate is 611 Mbps. For transmitter data rates less than 611 Mbps, oversampling must be applied at the transmitter. 3.
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1-24 UG-01143 2015.05.11 Channel PLL (CMU/CDR PLL) Channel PLL (CMU/CDR PLL) A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in clock data recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit PLLs when configured in clock multiplier unit (CMU) mode.
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Implementing Protocols in Arria 10 Transceivers 2 2015.05.11 UG-01143 Subscribe Send Feedback Transceiver Design IP Blocks Figure 2-1: Arria 10 Transceiver Design Fundamental Building Blocks Reset controller is used for resetting the transceiver channels. Transceiver Reset Controller (2) Transceiver PLL IP core provides a clock source to clock networks that drive the transceiver channels. In Arria 10 devices, PLL IP Core is separate from the transceiver PHY IP core.
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2-2 UG-01143 2015.05.11 Transceiver Design Flow Transceiver Design Flow Figure 2-2: Transceiver Design Flow Note: The design examples on the alterawiki page provide useful guidance for developing your own design. However, the content on the alterawiki page is not guaranteed by Altera.
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UG-01143 2015.05.11 Select and Instantiate the PHY IP Core 2-3 not have the option to set the speed grade. Specify the device family and speed grade when you create the Quartus II project. You can also instantiate the PHY IP directly to evaluate the various features. To instantiate a PHY IP: 1. 2. 3. 4. Open the Quartus II software. Click Tools > IP Catalog.
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2-4 UG-01143 2015.05.11 Configure the PHY IP Core Figure 2-3: Arria 10 Transceiver PHY Types Related Information Arria 10 Transceiver Protocols and PHY IP Support on page 2-10 Configure the PHY IP Core Configure the PHY IP core by selecting the valid parameters for your design. The valid parameter settings are different for each protocol. Refer to the appropriate protocol's section for selecting valid parameters for each protocol.
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UG-01143 2015.05.11 Generate the PHY IP Core 2-5 Related Information • Using the Arria 10 Transceiver Native PHY IP Core on page 2-17 For information on Native PHY IP.
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2-6 Select the PLL IP Core UG-01143 2015.05.11 To instantiate a PLL IP: 1. 2. 3. 4. Open the Quartus II software. Click Tools > IP Catalog. At the top of the IP Catalog window, select Arria 10 device family In IP Catalog, under Library > Basic Functions > Clocks, PLLs, and Resets > PLL choose the PLL IP (Arria 10 fPLL, Arria 10 Transceiver ATX PLL, or Arria 10 Transceiver CMU PLL) you want to include in your design and then click Add. 5. In the New IP Instance Dialog Box, provide the IP instance name.
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UG-01143 2015.05.11 Configure the PLL IP Core 2-7 Figure 2-4: Arria 10 Transceiver PLL Types Related Information PLLs on page 3-3 Configure the PLL IP Core Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.
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2-8 UG-01143 2015.05.11 Generate the PLL IP Core • fPLL IP Core on page 3-15 • CMU PLL IP Core on page 3-24 • Using PLLs and Clock Networks on page 3-49 Generate the PLL IP Core After configuring the PLL IP, complete the following steps to generate the PLL IP. 1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens. 2. In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL. 3.
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UG-01143 2015.05.11 Connect the PHY IP to the PLL IP and Reset Controller 2-9 Connect the PHY IP to the PLL IP and Reset Controller Connect the PHY IP, PLL IP, and the reset controller. Write the top level module to connect all the IP blocks. All of the I/O ports for each IP, can be seen in the .v file or .vhd, and in the _bb.v file.
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2-10 UG-01143 2015.05.11 Verify Design Functionality Related Information Quartus II Incremental Compilation for Hierarchical and Team-Based Design For more information about compilation details. Verify Design Functionality Simulate your design to verify the functionality of your design. For more details, refer to Simulating the Native Transceiver PHY IP Core section.
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UG-01143 2015.05.11 Arria 10 Transceiver Protocols and PHY IP Support 2-11 Protocol Transceiver IP PCS Support Transceiver Configuration Rule(15) Protocol Preset (16) 1000BASE-X Gigabit Ethernet Native PHY IP Standard GbE GIGE - 1.25 Gbps 1000BASE-X Gigabit Ethernet with 1588 Native PHY IP Standard GbE 1588 GIGE - 1.
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UG-01143 2015.05.11 Arria 10 Transceiver Protocols and PHY IP Support 2-13 Protocol Transceiver IP PCS Support Transceiver Configuration Rule(15) Protocol Preset (16) OTU-4 (100G) via OTL4.10/OIF SFI-S Native PHY IP Enhanced Basic (Enhanced PCS) SFI-S 64:64 4x11.3 Gbps OTU-3 (40G) via OTL3.4/ OIF SFI-5.2/SFI-5.
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2-14 UG-01143 2015.05.11 Arria 10 Transceiver Protocols and PHY IP Support Protocol Transceiver IP PCS Support Transceiver Configuration Rule(15) Protocol Preset (16) SONET STS-96 (5G) via OIF SFI-5.1s Native PHY IP Enhanced Basic/Custom (Standard PCS) SONET/SDH OC-96 SONET/SDH STS-48/ STM-16 (2.5G) via SFP/ TFI-5.1 Native PHY IP Standard Basic/Custom (Standard PCS) SONET/SDH OC-48 SONET/SDH STS-12/ STM-4 (0.622G) via SFP/ TFI-5.
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2-16 UG-01143 2015.05.11 Arria 10 Transceiver Protocols and PHY IP Support Protocol Transceiver IP PCS Support Transceiver Configuration Rule(15) Protocol Preset (16) SATA 3.0/2.0/1.0 and SAS 2.0/1.1/1.0 Native PHY IP Standard Basic/Custom (Standard PCS) SAS Gen2/Gen1.
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UG-01143 2015.05.11 Using the Arria 10 Transceiver Native PHY IP Core 2-17 Using the Arria 10 Transceiver Native PHY IP Core This section describes the use of the Altera-provided Arria 10 Transceiver Native PHY IP core. This IP core provides direct access to Arria 10 transceiver PHY features. Use the Transceiver Native PHY IP core to configure the transceiver PHY for your protocol implementa‐ tion. To instantiate the IP, click Tools > IP Catalog to select your IP core variation.
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2-20 UG-01143 2015.05.11 General and Datapath Parameters • Standard PCS • PCS Direct • Dynamic Reconfiguration Table 2-2: General and Datapath Options Parameter Value Description Message level for error rule violations warning Specifies the messaging level for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations.
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UG-01143 2015.05.11 General and Datapath Parameters Parameter Transceiver mode Value Description TX/RX Duplex Specifies the operational mode of the transceiver. TX Simplex • TX/RX Duplex : Specifies a single channel that supports both transmit and receive capabilities. • TX Simplex : Specifies a single channel that supports only transmission. • RX Simplex : Specifies a single channel that supports only reception. RX Simplex 2-21 The default is TX/RX Duplex.
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2-22 UG-01143 2015.05.11 General and Datapath Parameters Transceiver Configuration Setting Description Basic/Custom w /Rate Match (Standard PCS) Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules. CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto.
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2-24 UG-01143 2015.05.11 PMA Parameters Table 2-4: TX Bonding Options Parameter TX channel bonding mode Value Not bonded PMA only bonding PMA and PCS bonding Description Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew.
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UG-01143 2015.05.11 PMA Parameters 2-25 Table 2-5: TX PLL Options Parameter TX local clock division factor Value 1, 2, 4, 8 Description Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks. Number of TX 1, 2, 3 , 4 PLL clock inputs per channel Specifies the number of TX PLL clock inputs per channel.
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2-26 UG-01143 2015.05.11 PMA Parameters Parameter Value Enable tx_pma_ elecidle port On/Off Description Enables the tx_pma_elecidle port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express. Enable tx_pma_ On/Off qpipullup port (QPI) Enables the tx_pma_qpipullup control input port. Use this port only for Quick Path Interconnect (QPI) applications.
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UG-01143 2015.05.11 PMA Parameters Parameter PPM detector threshold Value 2-27 Description 100 Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock, exceeds this threshold value, the CDR loses lock. 300 500 The default value is 1000. 1000 Table 2-8: Equalization Parameters CTLE adaptation mode Value Manual Triggered Description Specifies the Continuous Time Linear Equaliza‐ tion (CTLE) operation mode.
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2-28 UG-01143 2015.05.11 PMA Parameters Parameters Value Number of fixed DFE taps 3,7 Description Specifies the number of fixed DFE taps. Select the number of taps depending on the loss in your transmission channel and the type of equalization required. Table 2-9: RX PMA Optional Ports Parameters Value Description Enable rx_pma_ On/Off clkout port Enables the optional rx_pma_clkout output clock. This port is the recovered parallel clock from the RX clock data recovery (CDR).
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UG-01143 2015.05.11 Enhanced PCS Parameters Parameters Value 2-29 Description Enable rx_is_ On/Off lockedtoref port Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal. Enable rx_set_ On/Off lockedtodata port and rx_set_ lockedtoref ports Enables the optional rx_set_lockedtodata and rx_set_ lockedtoref control input ports.
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2-30 UG-01143 2015.05.11 Enhanced PCS Parameters Parameter FPGA fabric / Enhanced PCS interface width Range 32 , 40 , 50 , 64 , 66 , 67 Description Specifies the interface width between the Enhanced PCS and the FPGA fabric. The 66-bit FPGA fabric to PCS interface width uses 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus.
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UG-01143 2015.05.11 Enhanced PCS Parameters 2-31 Table 2-11: Enhanced PCS TX FIFO Parameters Parameter Range Description TX FIFO Mode Phase-Compensation Specifies one of the following modes: • Phase Compensation: The TX FIFO compensates for Register the clock phase difference between the read clock (rx_ Interlaken clkout) and the write clocks (tx_coreclkin or tx_ clkout). TX FIFO write clock frequency and read clock Basic frequency depends on uneven gear ratios (like 64:40, Fast Register 64:32 etc.
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2-32 UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Range Description Enable tx_enh_fifo_ On / Off pfull port Enables the tx_enh_fifo_pfull port. This signal indicates when the TX FIFO reaches the specified partially full threshold. This signal is synchronous to tx_ coreclkin. Enable tx_enh_fifo_ On / Off empty port Enables the tx_enh_fifo_empty port. This signal indicates when the TX FIFO reaches the specified empty threshold. This is an asynchronous signal.
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UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Range 2-33 Description Enable RX FIFO alignment word deletion (Interlaken) On / Off When you turn on this option, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion. Enable RX FIFO control word deletion (Interlaken) On / Off When you turn on this option, Interlaken control word removal is enabled.
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2-34 UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Range Enable rx_enh_ On / Off fifo_align_clr port (Interlaken) Description Enables the rx_enh_fifo_align_clr input port. Only used for Interlaken. This signal is synchronous to rx_clkout. Table 2-13: Interlaken Frame Generator Parameters Parameter Range Description Enable On / Off Interlaken frame generator Enables the frame generator block of the Enhanced PCS.
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UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Range 2-35 Description Enable rx_enh_ On / Off frame_lock port Enables the rx_enh_frame_lock output port. When the Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has acheived metaframe delineation. This is an asynchronous output signal. Enable rx_enh_ frame_diag_ status port Enables the rx_enh_frame_diag_status output port.
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2-36 UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Enable rx_enh_ highber_clr_cnt port (10GBASE-R) Range Description On / Off Enables the rx_enh_highber_clr_cnt input port. For the 10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_ BAD_SH" state. This is an asynchronous signal.
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UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Enable RX descrambler (10GBASE-R/ Interlaken) Range On / Off 2-37 Description Enables the descrambler function. This option is available for Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios.
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2-38 UG-01143 2015.05.11 Enhanced PCS Parameters Parameter Range Description Enable RX data bitslip On / Off When you turn on this option, the Enhanced PCS RX block synchronizer operates in bitslip mode. When enabled, the rx_ bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS. Enable RX data polarity inversion On / Off When you turn on this option, the polarity of the RX data is inverted.
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UG-01143 2015.05.11 Standard PCS Parameters 2-39 • Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS on page 2-279 • Interlaken on page 2-76 • 10GBASE-R and 10GBASE-R 1588 • 10GBASE-KR PHY IP Core on page 2-125 • Enhanced PCS Ports on page 2-54 Standard PCS Parameters This section provides descriptions of the parameters that you can specify to customize the Standard PCS.
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2-40 UG-01143 2015.05.11 Standard PCS Parameters Table 2-24: TX and RX FIFO Parameters Parameter TX FIFO mode Range low_latency register_fifo fast_register RX FIFO mode Description Specifies the Standard PCS TX FIFO mode. The following modes are available: • low_latency: This mode adds 2-3 cycles of latency to the TX datapath. • register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS.
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UG-01143 2015.05.11 Standard PCS Parameters 2-41 Table 2-25: Byte Serializer and Deserializer Parameters Parameter Enable TX byte serializer Range Disabled Serialize x2 Serialize x4 Enable RX byte deserializer Disabled Deserialize x2 Deserialize x4 Description Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer.
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2-42 UG-01143 2015.05.11 Standard PCS Parameters Parameter Range Description RX rate match insert/delete +ve pattern (hex) User-specified 20 Specifies the +ve (positive) disparity value for the RX rate bit pattern match FIFO as a hexadecimal string. RX rate match insert/delete -ve pattern (hex) User-specified 20 Specifies the -ve (negative) disparity value for the RX rate bit pattern match FIFO as a hexadecimal string.
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UG-01143 2015.05.11 Standard PCS Parameters Parameter Range Number of word alignment patterns to achieve sync 0-255 Number of invalid words to lose sync 0-63 Number of valid data words to decrement error count 0-255 2-43 Description Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchro‐ nization lock. The default is 3.
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2-44 UG-01143 2015.05.11 Standard PCS Parameters Table 2-29: Bit Reversal and Polarity Inversion Parameter Range Description Enable TX bit reversal On / Off When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for seriali‐ zation. The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. During the operation of the circuit, this setting can be changed through dynamic reconfiguration.
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UG-01143 2015.05.11 Standard PCS Parameters 2-45 Parameter Range Description Enable rx_std_ byterev_ena port On / Off Enable RX polarity inversion On / Off When you turn on this option, the rx_std_polinv port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port. Enable rx_polinv port On / Off When you turn on this option, the rx_polinv input is enabled.
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2-46 UG-01143 2015.05.11 PCS Direct Parameter Range Enable PCIe pipe_rx_polarity port On / Off Description When you turn on this option, the pipe_rx_polarity input control port is enabled. You can use this option to control channel signal polarity for PCI Express configurations. When the Standard PCS is configured for PCIe, the assertion of this signal inverts the RX bit polarity. For other Transceiver configuration rules the optional rx_polinv port inverts the polarity of the RX bit stream.
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UG-01143 2015.05.11 Dynamic Reconfiguration Parameters 2-47 Parameter Value Description Enable Altera Debug Master Endpoint On/Off When you turn on this option, the Transceiver Native PHY IP includes an embedded Altera Debug Master Endpoint (ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
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2-48 UG-01143 2015.05.11 Dynamic Reconfiguration Parameters Parameter Value Description Generate MIF (Memory Initializa‐ tion File) On/Off When you turn on this option, the Transceiver Native PHY IP generates a MIF, _reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
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UG-01143 2015.05.11 PMA Ports 2-49 Parameter Value Description Clear all profiles - Clicking this button clears the Native PHY parameter settings for all the profiles. Refresh selected profile - Clicking this button is equivalent to clicking the “Load configuration from selected profile” and “Store configuration to selected profile” buttons in sequence.
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2-50 UG-01143 2015.05.11 PMA Ports Name tx_serial_clk1 Direction Clock Domain Description Inputs Clocks These are the serial clocks from the TX PLL. The frequency of these clocks depends on the data rate and clock division factor. These additional ports are enabled when you specify more than one TX PLL. Output Clock This clock is the low speed parallel clock from the TX PMA. It is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP core Parameter Editor.
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UG-01143 2015.05.11 PMA Ports Name tx_pma_ rxfound[-1:0] rx_ seriallpbken[ -1:0] Direction Clock Domain 2-51 Description Output Synchronous to rx_coreclkin or rx_clkout based on the configura‐ tion. This port is available if you turn on Enable tx_ rxfound_pma port (QPI) in the Transceiver Native PHY IP core Parameter Editor. When asserted, indicates that the receiver detect block in TX PMA has detected a receiver at the other end of the channel.
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2-52 UG-01143 2015.05.11 PMA Ports Name rx_pma_clkslip rx_pma_ qpipulldn[1:0] rx_is_lockedtodata[-1:0] rx_is_ lockedtoref[1:0] rx_set_ locktodata[1:0] rx_set_ locktoref[1:0] rx_ seriallpbken[ -1:0] rx_prbs_done[ -1:0] rx_prbs_err[1:0] Direction Clock Domain Description Output Clock A rising edge on this signal causes the RX deserializer to slip the serial data by one clock cycle 2 unit intervals (UI).
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UG-01143 2015.05.11 PMA Ports 2-53 Table 2-39: Calibration Status Ports Name Direction Clock Domain Description tx_cal_busy[-1:0] Output Asynchronous When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal will be asserted during calibration and will deassert after calibration is completed. You must hold the channel in reset until calibration completes.
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2-54 UG-01143 2015.05.11 Enhanced PCS Ports Enhanced PCS Ports Figure 2-7: Enhanced PCS Interfaces The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
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UG-01143 2015.05.11 Enhanced PCS Ports Name Direction Clock Domain 2-55 Description You must ground the data pins that are not active. For single width configuration, the following bits are active: • 32-bit FPGA fabric to PCS interface width: tx_ parallel_data[31:0]. Ground [127:32]. • 40-bit FPGA fabric to PCS interface width: tx_ parallel_data[39:0]. Ground [127:40]. • 63-bit FPGA fabric to PCS interface width: tx_ parallel_data[63:0] Ground [127:64].
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2-56 UG-01143 2015.05.11 Enhanced PCS Ports Name Direction Clock Domain Description sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe.
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UG-01143 2015.05.11 Enhanced PCS Ports Name unused_rx_ parallel_data Direction Output Output Clock Domain rx_clkout 2-57 Description This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_parallel_data. You can leave the unused data outputs floating or not connected.
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2-58 UG-01143 2015.05.11 Enhanced PCS Ports Name Direction Clock Domain tx_enh_fifo_ pfull[-1:0] Output tx_enh_fifo_ empty[-1:0] Output tx_clkout tx_enh_fifo_ pempty[-1:0] Output Asynchronous Description Synchronous to This signal gets asserted when the TX FIFO the clock reaches its partially full threshold. driving the write side of the FIFO (tx_coreclkin or tx_clkout) When asserted, indicates that the TX FIFO is empty. This signal gets asserted for 2 to 3 clock cycles.
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UG-01143 2015.05.11 Enhanced PCS Ports Name Direction Clock Domain 2-59 Description rx_enh_fifo_ empty[-1:0] Output Synchronous to the clock driving the read side of the FIFO (rx_ coreclkin or rx_clkout) When asserted, indicates that the RX FIFO is empty. rx_enh_fifo_ pempty[-1:0] Output Synchronous to the clock driving the read side of the FIFO (rx_ coreclkin or rx_clkout) When asserted, indicates that the RX FIFO has reached its specified partially empty threshold.
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2-60 UG-01143 2015.05.11 Enhanced PCS Ports Table 2-45: Interlaken Frame Generator, Synchronizer, and CRC32 Name Direction Clock Domain tx_enh_frame[-1:0] Output tx_clkout tx_enh_frame_diag_ status[ 2-1:0] Input tx_clkout Description Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe. Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]).
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UG-01143 2015.05.11 Enhanced PCS Ports Name Direction rx_enh_frame_diag_status[2 -1:0] Output Clock Domain rx_clkout 2-61 Description Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined: • Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.
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2-62 UG-01143 2015.05.11 Enhanced PCS TX and RX Control Ports Table 2-48: Gearbox Name Direction Clock Domain rx_bitslip[-1:0] Input rx_clkout tx_enh_bitslip[-1:0] Input rx_clkout Description The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. Keep the minimum interval between rx_bitslip pulses to at least 20 cycles. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.
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UG-01143 2015.05.11 Enhanced PCS TX and RX Control Ports 2-63 Enhanced PCS TX Control Port Bit Encodings Table 2-50: Bit Encodings for Interlaken Name Bit Functionality [1:0] [2] tx_control [7:3] [8] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. Inversion control A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity.
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2-64 UG-01143 2015.05.11 Enhanced PCS TX and RX Control Ports Table 2-53: Bit Encodings for Basic Double Width Mode For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header. Name tx_control Bit Functionality [1:0] Synchronous header [8:2] Unused [10:9] Synchronous header Description The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
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UG-01143 2015.05.11 Enhanced PCS TX and RX Control Ports 2-65 Enhanced PCS RX Control Port Bit Encodings Table 2-55: Bit Encodings for Interlaken Name rx_ control Bit Functionality Description [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. [2] Inversion control A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity.
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2-66 UG-01143 2015.05.
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UG-01143 2015.05.11 Enhanced PCS TX and RX Control Ports 2-67 Table 2-58: Bit Encodings for Basic Double Width Mode For basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous header. Name rx_control Bit Functionality Description [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word. [7:2] Unused [8] Synchronous header error status Active-high status signal that indicates a synchronous header error.
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2-68 UG-01143 2015.05.11 Standard PCS Ports Standard PCS Ports Figure 2-8: Transceiver Channel using the Standard PCS Ports Standard PCS ports will appear, if either one of the Transceiver Configuration modes is selected that uses Standard PCS or if Data Path Reconfiguration is selected even if the Transceiver Configuraion is not one of those that uses Standard PCS.
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UG-01143 2015.05.11 Standard PCS Ports Name Direction Clock Domain 2-69 Description This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of tx_parallel_data. Connect all these bits to 0. If you do not connect the unused data bits to 0, then TX parallel data may not be serialized correctly by the Native PHY IP core.
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2-70 UG-01143 2015.05.11 Standard PCS Ports Name rx_coreclkin Direction Input Clock Domain Clock Description RX parallel clock that drives the read side clock of the RX FIFO. Table 2-62: TX and RX FIFO Name Direction Clock Domain Description tx_std_pcfifo_ full[-1:0] Output Synchronous Indicates when the standard TX FIFO is full.
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UG-01143 2015.05.11 Standard PCS Ports Name Direction Clock Domain 2-71 Description rx_std_rmfifo_ empty[-1:0] Output Asynchronous Rate match FIFO empty flag. When asserted, match FIFO is empty. You must synchronize this signal. This port is only used for GigE mode. rx_rmfifostatus[ -1:0] Output Asynchronous Indicates FIFO status.
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2-72 UG-01143 2015.05.11 Standard PCS Ports Name rx_errdetect[ /-1:0] rx_disperr[/ -1:0] rx_runningdisp[ /-1:0] rx_patterndetect[/1:0] rx_syncstatus[ /-1:0] Direction Output Clock Domain Description Synchronous to the clock driving the read side of the FIFO (rx_ coreclkin or rx_clkout) When asserted, indicates a code group violation detected on the received code group.
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UG-01143 2015.05.11 Standard PCS Ports Name tx_std_bitslipboundarysel[5 -1:0] rx_std_bitslipboundarysel[5 -1:0] rx_std_wa_patternalign[-1:0] Direction Clock Domain 2-73 Description Input Asynchronous Bitslip boundary selection signal. Specifies the number of bits that the TX bit slipper must slip. Output Asynchronous This port is used in deterministic latency word aligner mode. It reports the number of bits that the RX block slipped to achieve deterministic latency.
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2-74 UG-01143 2015.05.11 Standard PCS Ports Table 2-66: Bit Reversal and Polarity Inversion Name Direction Clock Domain Description rx_std_byterev_ena[-1:0] Input Asynchro‐ nous This control signal is available when the PMA width is 16 or 20 bits. When asserted, enables byte reversal on the RX interface. Used if the MSB and LSB of the transmitted data are erroneously swapped. rx_std_bitrev_ena[-1:0] Input Asynchro‐ nous When asserted, enables bit reversal on the RX interface.
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UG-01143 2015.05.11 IP Core File Locations 2-75 IP Core File Locations When you generate your Transceiver Native PHY IP, the Quartus® II software generates the HDL files that define your instance of the IP. In addition, the Quartus II software generates an example Tcl script to compile and simulate your design in the ModelSim simulator. It also generates simulation scripts for Synopsys VCS, Aldec Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.
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2-76 UG-01143 2015.05.11 Interlaken Table 2-67: Transceiver Native PHY Files and Directories File Name Description The top-level project directory. .v or .vhd The top-level design file. .qip A list of all files necessary for Quartus II compila‐ tion. .bsf A Block Symbol File (.bsf) for your Transceiver Native PHY instance. // The directory that stores the HDL files that define the Transceiver Native PHY IP.
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UG-01143 2015.05.11 2-77 Interlaken Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst semantics include integrity checking and per logical channel flow control. The Interlaken interface is supported with 1 to 48 lanes running at data rates up to 17.
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2-78 UG-01143 2015.05.11 Metaframe Format and Framing Layer Control Word Related Information • Interlaken Protocol Definition v1.2 • Interlaken Look-Aside Protocol Definition, v1.1 Metaframe Format and Framing Layer Control Word The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words. However, for stability and performance, Altera recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times.
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UG-01143 2015.05.11 Interlaken Configuration Clocking and Bonding 2-79 The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is defined by the Interlaken specification as: • Bit 1 (Bit 33): Lane health • 1: Lane is healthy • 0: Lane is not healthy • Bit 0 (Bit 32): Link health • 1: Link is healthy • 0: Link is not healthy The tx_enh_frame_diag_status[1:0] input from the FPGA fabric is inserted into the Status field each time a DIAG word is created by the framing generator.
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2-80 UG-01143 2015.05.11 PLL Feedback Compensation Clock Bonding Scenario Because of xN clock network skew, the maximum achievable data rate decreases when TX channels span several transceiver banks. Figure 2-15: 10X12.5 Gbps xN Bonding Native PHY Instance (10 Ch Bonded 12.5 Gbps) Transceiver PLL Instance (6.
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UG-01143 2015.05.11 PLL Feedback Compensation Clock Bonding Scenario 2-81 network. In feedback compensation bonding, the separate x6 clocks are in phase and frequency aligned with each other. One PLL from each transceiver bank drives the clock to master CGB. The CGB then drives these clocks to the TX channels that reside in the same bank only. In xN bonding, all channels are driven by the xN clock network. The data rate decrease imposed by xN bonding does not apply to PLL feedback compensation bonding.
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2-82 UG-01143 2015.05.11 TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port signals are provided to the FPGA fabric. Connect these signals to the MAC layer as required by the protocol.
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2-84 UG-01143 2015.05.11 RX Multi-lane FIFO Deskew State Machine Figure 2-18: TX FIFO Pre-fill (6-lane Interface) Deassert tx_digitalreset tx_digitalreset 3f 00 tx_enh_data_valid 00 tx_enh_fifo_full 00 tx_enh_fifo_pfull 00 tx_enh_fifo_empty tx_enh_fifo_pempty tx_enh_fifo_cnt tx_enh_frame tx_enh_frame_burst_en 3f 00 3f 3f 3f 3f 000000 00 00 00 1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e...
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UG-01143 2015.05.11 RX Multi-lane FIFO Deskew State Machine 2-85 Implement a multi-lane alignment deskew state machine to control the RX FIFO operation based on available RX FIFO status flags and control signals.
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2-86 UG-01143 2015.05.11 How to Implement Interlaken in Arria 10 Transceivers Figure 2-21: RX FIFO Deskew After deskew is successful, the user logic asserts rd_en for all lanes to start reading data from the RX FIFO.
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2-88 UG-01143 2015.05.11 How to Implement Interlaken in Arria 10 Transceivers 7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation. 8. Connect the Native PHY IP to the PLL IP and the reset controller. Figure 2-23: Connection Guidelines for an Interlaken PHY Design This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Altera Wiki website.
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UG-01143 2015.05.11 How to Implement Interlaken in Arria 10 Transceivers 2-89 Figure 2-24: 24 Lanes Bonded Interlaken Link, TX Direction To show more details, three different time segments are shown with the same zoom level.
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2-90 UG-01143 2015.05.11 Design Example • Resetting Transceiver Channels on page 4-1 Reset controller general information and implementation details • Enhanced PCS Ports on page 2-54 For detailed information about the available ports in the Interlaken protocol. Design Example Altera provides a PHY layer-only design example to help you integrate an Interlaken PHY into your complete design. The TX soft bonding logic is included in the design example.
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for Interlaken Parameter Provide separate interface for each channel 2-91 Value On / Off Table 2-69: TX PMA Parameters Parameter TX channel bonding mode Value Not bonded PMA-only bonding PMA and PCS bonding PCS TX channel bonding master If TX channel bonding mode is set to PMA and PCS bonding, then: Auto, 0, 1, 2, 3,...
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for Interlaken 2-93 Table 2-71: Enhanced PCS Parameters Parameter Enhanced PCS / PMA interface width Value 32, 40, 64 FPGA fabric / Enhanced PCS interface 67 width Enable 'Enhanced PCS' low latency mode Allowed when the PMA interface width is 32 and preset variations for data rate is 10.3125 Gbps or 6.
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UG-01143 2015.05.11 Ethernet Parameter 2-97 Value Generate SystemVerilog package file On / Off Generate C header file On / Off Generate MIF (Memory Intialization File) On / Off Table 2-81: Generation Options Parameters Parameter Value Generate parameter documentation file On / Off Ethernet The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates.
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~~2-98 UG-01143 2015.05.11 Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 Figure 2-26: GbE PHY Connection to IEEE 802.~~
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2-100 UG-01143 2015.05.11 8B/10B Encoding for GbE, GbE with IEEE 1588v2 8B/10B Encoding for GbE, GbE with IEEE 1588v2 The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is sent to the PMA. The IEEE 802.3 specification requires GbE to transmit idle ordered sets (/I/) continuously and repetitively whenever the gigabit media-independent interface (GMII) is idle.
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UG-01143 2015.05.11 Word Alignment for GbE, GbE with IEEE 1588v2 2-101 Figure 2-29: Reset Condition n n+1 n+2 n+3 n+4 K28.5 Dx.y Dx.y K28.5 Dx.y clock tx_digitalreset tx_parallel_data K28.5 xxx K28.5 K28.5 K28.5 Dx.y K28.5 Dx.y User transmitted synchronization sequence Automatically transmitted /K28.
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UG-01143 2015.05.11 2-103 Rate Match FIFO for GbE Related Information 8B/10B Decoder on page 5-50 Rate Match FIFO for GbE The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125 MHz ± 100 ppm difference. Note: 200 ppm total is only true if calculated as (125 MHz + 100 ppm) - (125 MHz - 100 ppm) = 200 ppm. By contrast, (125 MHz + 0 ppm) - (125 MHz - 200 ppm) is out of specification.
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2-104 UG-01143 2015.05.11 How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts the rx_std_rmfifo_full flag for at least two recovered clock cycles to indicate rate match FIFO full. The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer.
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UG-01143 2015.05.11 How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers 2-105 Before you begin You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol. 1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog. Refer to Select and Instantiate the PHY IP Core on page 2-2. 2.
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2-106 UG-01143 2015.05.11 Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 You can use your own reset controller or use the Native PHY Reset Controller IP core. 7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in the figure below to connect the ports.
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 2-107 Table 2-83: General and Datapath Options The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
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2-110 UG-01143 2015.05.11 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants Parameters RX word aligner mode Value Synchronous state machine RX word aligner pattern length 7, 10 RX word aligner pattern (hex) 0x000000000000007c (Comma) (for 7bit aligner pattern length), 0x000000000000017c (/K28.
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UG-01143 2015.05.11 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants 2-111 The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) that interfaces with the Media Access Control (MAC), which has the optional Reconciliation Sub-layer (RS). Figure 2-38: 10GBASE-R PHY as Part of the IEEE802.
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2-112 UG-01143 2015.05.11 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants Figure 2-39: Transceiver Channel Datapath and Clocking for 10GBASE-R FPGA Fabric Transmitter Enhanced PCS TX Data & Control Enhanced PCS TX FIFO (3) Interlaken Frame Generator Interlaken CRC32 Generator 64 64 + 8 PRP Generator Parallel Clock tx_coreclkin PRBS Generator 66 64B/66B Encoder and TX SM Scrambler (self sync) mode Interlaken Disparity Generator TX Gearbox Serializer 10.
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UG-01143 2015.05.11 2-113 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants • Data acquisition • Test equipment • Measurement The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.
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2-114 UG-01143 2015.05.11 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants The RX FEC sublayer: • • • • • Receives data from the PMA Performs descrambling Achieves FEC framing synchronization Decodes and corrects data where necessary and possible Recodes 64b/66b words and sends the data to the PCS The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS and PMA sublayers of the 10GBASE-R physical layer.
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UG-01143 2015.05.11 The XGMII Clocking Scheme in 10GBASE-R 2-115 Figure 2-42: Clock Generation and Distribution for 10GBASE-R with FEC Support Example using a 64-bit PCS-PMA interface width. 10GBASE-R Hard IP Transceiver Channel TX 64 Bit Data 8 Bit Control 64 TX PCS TX PMA 161.13 MHz TX PLL 10.3125 Gbps Serial pll_ref_clk 644.53125 MHz RX 64 Bit Data 8 Bit Control 156.25 MHz rx_coreclkin 64 RX PCS 161.13 MHz RX PMA 10.
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2-116 UG-01143 2015.05.11 TX FIFO and RX FIFO Figure 2-43: XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R Configurations XGMII Transfer (DDR) Interface Clock (156.25) MHz TXD/RXD[31:0] D0 D1 D2 D3 D4 D5 D6 TXC/RXC[3:0] C0 C1 C2 C3 C4 C5 C6 Transceiver Interface (SDR) Interface Clock (156.25) MHz TXD/RXD[63:0] {D1, D0} {D3, D2} {D5, D4} TXC/RXC[7:0] {C1, C0} {C3, C2} {C5, C4} Note: Clause 46 of the IEEE 802.
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~~UG-01143 2015.05.11 How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R...~~
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2-118 UG-01143 2015.05.11 How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R... Figure 2-44: Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Generating the IP core creates signals and ports based on your parameter settings.
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~~UG-01143 2015.05.11 How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R...~~
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2-120 UG-01143 2015.05.11 Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE... Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Table 2-87: General and Datapath Parameters The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath options to customize the transceiver.
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE... Parameter 2-121 Range Selected CDR reference clock frequency 322.265625 MHz and 644.53125 MHz PPM detector threshold 62.5, 100,125, 200, 250, 300, 500, 1000 CTLE adaptation mode Manual Triggered Decision feedback equalization mode disabled Table 2-90: Enhanced PCS Parameters Parameter Enhanced PCS/PMA interface width Range 32, 40, 64 Note: 10GBASE-R with KR FEC allows 64 only.
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~~2-122 UG-01143 2015.05.11 Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE...~~
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~~UG-01143 2015.05.11 Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2...~~
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2-124 UG-01143 2015.05.11 Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2... Figure 2-48: Block Lock Assertion This figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation. rx_parallel_data rx_control tx_parallel_data tx_control rx_enh_highber rx_ready rx_enh_block_lock 0100009C0100009Ch 0707070707070707h 11h FFh 0707070707070707h FFh 0h 1h 0h 1h The following figures show Idle insertion and deletion.
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UG-01143 2015.05.11 10GBASE-KR PHY IP Core 2-125 10GBASE-KR PHY IP Core The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet standards: • Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3 2008 Standard. The 10GBASE-KR Ethernet PHY MegaCore Function can auto negotiate between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC. • 10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the IEEE 802.3 2008 Standard.
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2-126 UG-01143 2015.05.11 10GBASE-KR Functional Description The following table shows the typical expected resource utilization for selected configurations using the Quartus II software v15.0 for Arria 10 devices. The numbers of ALMs and logic registers are rounded up to the nearest 100.
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UG-01143 2015.05.11 10GBASE-KR Functional Description 2-127 The 10GBASE-KR PHY IP core includes the following components: Standard and Enhanced PCS Datapaths The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support 1G, 10G protocols and FEC. Auto Negotiation, IEEE 802.
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2-128 UG-01143 2015.05.11 Parameterizing the 10GBASE-KR PHY Figure 2-53: Reconfiguration Block Details MGMT_CLK (2) rcfg_data rcfg_data rcfg_data PCS Reconfiguration Interface PCS Controller rcfg_data (1) Avalon-MM Bus Avalon-MM Bus Avalon-MM Decoder PMA Controller HSSI Reconfiguration Requests Avalon-MM Bus TX EQ Controller PMA Reconfiguration Interface DFE Controller Avalon-MM reconfig_busy Signal CTLE Controller Notes: 1. rcfg = Reconfiguration 2.
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UG-01143 2015.05.11 General Options 2-129 Related Information • 10GBASE-R Parameters on page 2-130 • 10GBASE-KR Auto-Negotiation and Link Training Parameters on page 2-131 General Options The General Options allow you to specify options common to 10GBASE-KR mode. Table 2-100: General Options Parameters Parameter Name Options Description Enable internal PCS reconfigura‐ On tion logic Off This parameter is only an option when SYNTH_ SEQ = 0.
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2-130 UG-01143 2015.05.11 10GBASE-R Parameters Parameter Name Enable rx_clkout port Options On When you turn on this parameter, the rx_ clkout port is enabled. Refer to the clock and Off Enable Hard PRBS support reset signals section for more information about this port. On When you turn on this parameter, you enable the Hard PRBS data generation and checking logic in the Native PHY. Off Reference clock frequency 644.53125 MHz 322.
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UG-01143 2015.05.11 10GBASE-KR Auto-Negotiation and Link Training Parameters 2-131 Table 2-102: FEC Options Parameter Name Include FEC sublayer Options Description On When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS. Off 10GBASE-KR Auto-Negotiation and Link Training Parameters Table 2-103: Auto Negotiation and Link Training Settings Name AN_PAUSE Pause Ability Range 0-8 Description Depends upon MAC.
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2-132 UG-01143 2015.05.11 10GBASE-KR Optional Parameters 10GBASE-KR Optional Parameters Table 2-104: Optional Parameters In the following table, the exact correspondence between numerical values and voltages is pending characterization of the Native PHY. Name BERWIDTH Width of the Bit Error Counter PHY Management clock (MGMT_CLK) frequency in MHz Value Description 4-10 This selection sets the size for the counter of errors expected during each step of the link training.
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UG-01143 2015.05.11 10GBASE-KR PHY Interfaces Name INITMAINVAL Init VOD tap Value INITPOSTVAL Init Post tap Value INITPREVAL Init Pre tap Value Value 2-133 Description Specifies the initial VOD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3ap– 2007. The default value is 25. 0-31 Specifies the initial Post-tap value. The default value is 22. 0-38 Specifies the initial Pre-tap value. The default value is 3.
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2-134 UG-01143 2015.05.11 Clock and Reset Interfaces Clock and Reset Interfaces Table 2-105: Clock and Reset Signals Signal Name Direction Description tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz. tx_serial_clk_1g Input High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625 MHz.
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UG-01143 2015.05.11 Data Interfaces Signal Name Direction 2-135 Description rx_analogreset Input Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk. rx_digitalreset Input Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk. usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfigura‐ tion, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk.
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2-136 UG-01143 2015.05.11 XGMII Mapping to Standard SDR XGMII Data Signal Name xgmii_rx_clk Direction Input Clock Domain Clock signal Description Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_div_clkout ; however, Altera recommends that you connect it to a PLL for use with the Triple Speed Ethernet MegaCore function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.
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~~PAGE 169~~
2-138 UG-01143 2015.05.11 Dynamic Reconfiguration Interface Signal Name led_an rx_block_lock Direction Output Output Clock Domain Description Synchronous to rx_ Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes. clkout Synchronous to rx_ Asserted to indicate that the block synchronizer has established synchronization.
~~PAGE 170~~
UG-01143 2015.05.11 Avalon-MM Register Interface Signal Name start_pcs_ reconfig Direction Input Clock Domain 2-139 Description Synchronous to mgmt_ When asserted, initiates reconfiguration of the PCS. Sampled with the mgmt_clk. This signal is only exposed under the following condition: clk • Turn on Enable internal PCS reconfiguration logic mode_1g_ 10gbar Input Synchronous to mgmt_ This signal selects either the 1G or 10G tx-paralleldata going to the PCS.
~~PAGE 171~~
2-140 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions 10GBASE-KR PHY Register Definitions The Avalon-MM slave interface signals provide access to the control and status registers. The following table specifies the control and status registers that you can access over the Avalon-MM PHY management interface. A single address space provides access to all registers. Note: Unless otherwise indicated, the default value of all registers is 0.
~~PAGE 172~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions 2-141 Table 2-113: 10GBASE-KR Register Definitions Word Addr Bit R/W Name 0 RW Reset SEQ 1 RW Disable AN Timer 2 RW Disable LF Timer 3 RW fail_lt_if_ber 7:4 RW SEQ Force Mode[3:0] 0x4B0 Description When set to 1, resets the 10GBASE-KR sequencer (auto rate detect logic), initiates a PCS reconfigura‐ tion, and may restart Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode).
~~PAGE 173~~
2-142 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 0 R SEQ Link Ready 1 R SEQ AN timeout 2 R SEQ LT timeout 13:8 R SEQ Reconfig Mode[5:0] 0x4B5 to 0x4BF Altera Corporation When asserted, the sequencer is indicating that the link is ready. When asserted, the sequencer has had an Auto Negotiation timeout. This bit is latched and is reset when the sequencer restarts Auto Negotiation. When set, indicates that the Sequencer has had a timeout.
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UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 0 RW AN enable 1 RW AN base pages ctrl 2 RW AN next pages ctrl 3 RW 4 RW 5 RW 0x4C0 Local device remote fault Force TX nonce value Override AN Parameters Enable 0 RW Reset AN 4 RW Restart AN TX SM 8 RW AN Next Page 0x4C1 Implementing Protocols in Arria 10 Transceivers Send Feedback 2-143 Description When set to 1, enables Auto Negotiation function. The default value is 1.
~~PAGE 175~~
2-144 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 1 RO AN page received 2 RO AN Complete 3 RO AN ADV Remote Fault 4 RO AN RX SM Idle 5 RO AN Ability 6 RO AN Status 7 RO LP AN Ability 0x4C2 Altera Corporation Description When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more informa‐ tion, refer to 7.1.6 in Clause 73.8 of IEEE 802.3ap2007.
~~PAGE 176~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 8 RO 9 RO 17:12 RO 0x4C2 Name FEC negotiated – enable FEC from SEQ Seq AN Failure KR AN Link Ready[5:0] Description When set to 1, PHY is negotiated to perform FEC. When set to 0, PHY is not negotiated to perform FEC. When set to 1, a sequencer Auto Negotiation failure has been detected. When set to 0, an Auto Negotiation failure has not been detected.
~~PAGE 177~~
2-146 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 15:0 R/W RW Name User base page low Description The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages ctrl bit is set.
~~PAGE 178~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr 0x4C5 Bit 15:0 R/W RW Name User Next page low 2-147 Description The Auto Negotiation TX state machine uses these bits if the AN Next Page control bit is set. The following bits are defined: • • • • • [15]: next page bit [14]: ACK controlled by the state machine [13]: Message Page (MP) bit [12]: ACK2 bit [11]: Toggle bit For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
~~PAGE 179~~
2-148 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr 0x4C9 Bit 15:0 R/W RO Name LP Next page low Description The AN RX state machine receives these bits from the link partner. The following bits are defined: • [15]: Next page bit • [14]: ACK which is controlled by the state machine • [13]: MP bit • [12] ACK2 bit • [11] Toggle bit For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
~~PAGE 180~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W Name 0 RW 1 RW dis_max_wait_tmr 2 RW quick_mode 3 RW pass_one 7:4 RW main_step_cnt [3:0] 11:8 RW prpo_step_cnt [3:0] Link Training enable 0x4D0 Implementing Protocols in Arria 10 Transceivers Send Feedback 2-149 Description When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR startup protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.
~~PAGE 181~~
2-150 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 14:12 R/W RW Name equal_cnt [2:0] Description Adds hysteresis to the error count to avoid local minimums. The following values are defined: • • • • • • • • 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 16 111 = reserved The default value is 010.
~~PAGE 182~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 19:18 R/W RW Name Ctle depth Description When using CTLE fine-grained tuning, determines where to set final value in case of a tie. The following values are defined: • • • • 21:20 RW rx_ctle_mode 2-151 00 = at lower tie 01 = 25% to upper tie 10 = 50% between lower and upper 11 = at upper tie Defines at what point to enable the RX CTLE in the adaptation algorithm.
~~PAGE 183~~
2-152 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit R/W 0 RO 1 RO 2 RO 3 RO 4 RO 5 RO 6 RO 7 RO 0x4D2 Altera Corporation Name Link Trained Receiver status Link Training Frame lock Link Training Start-up protocol status Link Training failure Link Training Error Link Training Frame lock Error RXEQ Frame Lock Loss CTLE Fine-grained Tuning Error Description When set to 1, the receiver is trained and is ready to receive data.
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UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 9:0 R/W RW Name ber_time_frames 2-153 Description Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_ frames is 0.The following values are defined: • A value of 2 is about 103 bytes • A value of 20 is about 104 bytes • A value of 200 is about 105 bytes The default value for simulation is 2'b11. The default value for hardware is 0.
~~PAGE 185~~
2-154 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 5:0 R/W RO or RW Name LD coefficient update[5:0] Description Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writeable.
~~PAGE 186~~
UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 13:8 R/W RO Name LD coefficient status[5:0] 2-155 Description Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel.
~~PAGE 187~~
2-156 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 21:16 R/W RO or RW Name LP coefficient update[5:0] Description Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel. Normally the bits in this register are read only; however, when training is disabled by setting low the KR Training enable control bit, these bits become writeable.
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~~PAGE 189~~
2-158 UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr 0x4D5 Altera Corporation Bit R/W Name 27:24 R RXEQ CTLE Setting 29:28 R RXEQ CTLE Mode 31:30 R RXEQ DFE Mode Description Most recent ctle_rc setting sent to the reconfig bundle during RX equalization. Most recent ctle_mode setting sent to the reconfig bundle during RX equalization. Most recent dfe_mode setting sent tothe reconfig bundle during RX equalization.
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UG-01143 2015.05.11 10GBASE-KR PHY Register Definitions Word Addr Bit 4:0 R/W RW Name LT VODMAX ovrd 2-159 Description Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only affects the local device TX output for the channel specified. This value must be greater than the INITMAINVAL parameter for proper operation. Note this will also override the PREMAINVAL parameter value.
~~PAGE 191~~
~~2-160 UG-01143 2015.05.11 Hard Transceiver PHY Registers Word Addr Bit R/W 0x4D6 to 0x4FF Name Reserved for 40G KR Description Left empty for address compatibility with 40G MAC+PHY KR solution.~~
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UG-01143 2015.05.11 Creating a 10GBASE-KR Design 2-161 Table 2-116: PMA Registers Address 0x444 0x461 Bit R/W Name 1 RW reset_tx_digital Writing a 1 asserts the internal TX digital reset signal. You must write a 0 to clear the reset condition. 2 RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted. You must write a 0 to clear the reset condition. 3 RW reset_rx_digital Writing a 1 causes the internal RX digital reset signal to be asserted.
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UG-01143 2015.05.11 Simulation Support 2-163 Related Information • Arria 10 Transceiver PHY Design Examples • 10-Gbps Ethernet MAC MegaCore Function User Guide. For more information about latency in the MAC as part of the Precision Time Protocol implementa‐ tion.
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2-164 UG-01143 2015.05.11 1G/10GbE PHY Release Information Figure 2-56: Top Level Modules of the 1G/10GbE PHY MegaCore Function The Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data. Altera Device with 10.3125-Gbps Transceivers 1G/10Gb Ethernet PHY MegaCore Function Native PHY Hard IP TX XGMII Data @156.
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UG-01143 2015.05.11 1G/10GbE PHY Performance and Resource Utilization Item 2-165 Description Release Date May 2015 Ordering Codes IP-1G10GBASER (primary) IPR-1G10GBASER (renewal code) Product ID 0107 Vendor ID 6AF7 1G/10GbE PHY Performance and Resource Utilization This topic provides performance and resource utilization for the 1G/10GbE PHY IP core in Arria 10 devices.
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UG-01143 2015.05.11 Clock and Reset Interfaces 2-167 information in the MAC as part of the Precision Time Protocol implementation, refer to the 10-Gbps Ethernet MAC MegaCore Function User Guide. Reconfiguration Block The reconfiguration logic performs the Avalon-MM writes to the PHY for both PCS and PMA reconfigu‐ ration. The following figure shows the details of the reconfiguration blocks. The Avalon-MM master accepts requests from the PMA or PCS controller.
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2-168 UG-01143 2015.05.11 Clock and Reset Interfaces You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of the MAC data rate. You can generate the 156.
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UG-01143 2015.05.11 Clock and Reset Interfaces Signal Name Direction 2-169 Description rx_cdr_refclk_1g Input The RX 1G PLL reference clock to drive the RX HSSI circuits. Connected to the rx_cdr_refclk[1] input of the native PHY. mgmt_clk Input Avalon-MM clock and control system clock. Its frequency range is 100 MHz to 125 MHz. mgmt_clk_reset Input When asserted, it resets the whole PHY. xgmii_tx_clk Input Clock for XGMII TX interface with MAC. Can be connected to tx_div_clkout.
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2-170 UG-01143 2015.05.11 Parameterizing the 1G/10GbE PHY Signal Name Direction Description rx_div_clk Output This is the receive div33 clock, which is recovered from the received data. It drives the Auto Negotia‐ tion (AN) and Link Training (LT) logic and is sourced from the Native PHY rx_pma_div_clkout port. Note: Use tx_clkout or xgmii_rx_clk for 10G TX datapath clocking. If the PHY is reconfig‐ ured to 1G mode, the frequency will change. Its frequency is 125, 156.25, or 312.5 MHz.
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UG-01143 2015.05.11 General Options 2-171 Related Information • • • • • General Options on page 2-129 10GBASE-R Parameters on page 2-130 10M/100M/1Gb Ethernet Parameters on page 2-173 Speed Detection Parameters on page 2-173 PHY Analog Parameters on page 2-174 General Options The General Options allow you to specify options common to 10GBASE-KR mode.
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2-172 UG-01143 2015.05.11 10GBASE-R Parameters Parameter Name Enable tx_clkout port Options On When you turn on this parameter, the tx_ clkout port is enabled. Refer to the clock and Off Enable rx_clkout port reset signals section for more information about this port. On When you turn on this parameter, the rx_ clkout port is enabled. Refer to the clock and reset signals section for more information about this port.
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UG-01143 2015.05.11 10M/100M/1Gb Ethernet Parameters Parameter Name Enable additional control and status pins Options On 2-173 Description When you turn on this parameter, the core includes the rx_block_lock and rx_hi_ber ports. Off Table 2-122: FEC Options Parameter Name Include FEC sublayer Options On Description When you turn on this parameter, the core includes logic to implement FEC and a soft 10GBASE-R PCS.
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2-174 UG-01143 2015.05.11 PHY Analog Parameters Table 2-124: Speed Detection Parameter Name Options Enable automatic speed detection On Avalon-MM clock frequency Link fail inhibit time for 10Gb Ethernet Link fail inhibit time for 1Gb Ethernet Description Off When you turn this option On, the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able to detect AN data.
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~~PAGE 207~~
2-176 UG-01143 2015.05.11 Clock and Reset Interfaces Clock and Reset Interfaces Table 2-125: Clock and Reset Signals Signal Name Direction Description tx_serial_clk_10g Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The frequency of this clock is 5.15625 GHz. tx_serial_clk_1g Input High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock is not required if GbE is not used. The frequency of this clock is 625 MHz.
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UG-01143 2015.05.11 Data Interfaces Signal Name Direction 2-177 Description rx_analogreset Input Resets the analog RX portion of the transceiver PHY. Synchronous to mgmt_clk. rx_digitalreset Input Resets the digital RX portion of the transceiver PHY. Synchronous to mgmt_clk. usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfigura‐ tion, and may restart AN, LT or both if these modes are enabled. Synchronous to mgmt_clk.
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2-178 UG-01143 2015.05.11 XGMII Mapping to Standard SDR XGMII Data Signal Name xgmii_rx_clk Direction Input Clock Domain Clock signal Description Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_div_clkout ; however, Altera recommends that you connect it to a PLL for use with the Triple Speed Ethernet MegaCore function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.
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2-180 UG-01143 2015.05.11 Serial Data Interface Signal Name Direction Description led_char_err Output 10-bit character error. Asserted for one rx_ clkout_1g cycle when an erroneous 10-bit character is detected. Synchronous to mgmt_ clk. led_link Output When asserted, this signal indicates successful link synchronization. Synchro‐ nous to mgmt_clk. led_disp_err Output When asserted, this signal indicates a 10-bit running disparity error.
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UG-01143 2015.05.11 Dynamic Reconfiguration Interface Signal Name rx_block_lock Direction Output Clock Domain Description Synchronous to rx_ Asserted to indicate that the block synchronizer has established synchronization. clkout rx_hi_ber Output Synchronous to rx_ Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4. clkout rx_is_ lockedtodata tx_cal_busy Output Asynchronous signal When asserted, indicates the RX channel is locked to input data.
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2-182 UG-01143 2015.05.11 Avalon-MM Register Interface Signal Name mode_1g_ 10gbar Direction Input Clock Domain Description Synchronous to mgmt_ This signal selects either the 1G or 10G tx-paralleldata going to the PCS. It is only used for the 1G/ 10G application (variant) under the following circumstances: clk • the Sequencer (auto-rate detect) is not enabled • 1G mode is enabled Avalon-MM Register Interface The Avalon-MM slave interface signals provide access to all registers.
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~~UG-01143 2015.05.11 Register Definitions 2-183 Note: Do not write to any register that is not specified.~~
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2-184 UG-01143 2015.05.11 Register Definitions Table 2-134: 1G/10GbE Register Definitions Word Addr Bit R/W Name 0 RW Reset SEQ 1 RW Disable AN Timer 2 RW Disable LF Timer 3 RW fail_lt_if_ber 7:4 RW SEQ Force Mode[2:0] 0x4 B0 Description When set to 1, resets the 10GBASE-KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are enabled (10GBASE-KR mode).
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UG-01143 2015.05.11 Register Definitions Word Addr Bit R/W Name Description 0 R SEQ Link Ready 1 R SEQ AN timeout 2 R SEQ LT timeout When set, indicates that the sequencer has had a timeout. 13:8 R SEQ Reconfig Mode[5:0] Specifies the sequencer mode for PCS reconfiguration. The following modes are defined: When asserted, the sequencer indicates the link is ready. When asserted, the sequencer has had an AN timeout. This bit is latched and is reset when the sequencer restarts AN.
~~PAGE 217~~
2-186 UG-01143 2015.05.11 Register Definitions Word Addr Bit R/W Name 0 RW AN enable 1 RW AN base pages ctrl 2 RW AN next pages ctrl 3 RW 4 RW 5 RW 0x4 C0 0x4 C1 Local device remote fault Force TX nonce value Override AN Parameters Enable 0 RW Reset AN 4 RW Restart AN TX SM 8 RW AN Next Page Altera Corporation Description When set to 1, enables the AN function. The default value is 1. For additional information, refer to bit 7.0.12 in Clause 73.
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UG-01143 2015.05.11 Register Definitions Word Addr 0x4 C2 Bit R/W Name 1 RO AN page received 2 RO AN Complete 3 RO AN ADV Remote Fault 4 RO AN RX SM Idle 5 RO AN Ability 6 RO AN Status 7 RO LP AN Ability 8 RO 9 RO 17:12 RO FEC negotiated – enable FEC from SEQ Seq AN Failure KR AN Link Ready[5:0] 0x4 C2 Implementing Protocols in Arria 10 Transceivers Send Feedback 2-187 Description When set to 1, a page has been received. When 0, a page has not been received.
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2-188 UG-01143 2015.05.11 Register Definitions Word Addr Bit 15:0 R/W RW Name User base page low Description The AN TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined: • • • • • • [15]: Next page bit [14]: ACK, controlled by the SM [13]: Remote Fault bit [12:10]: Pause bits [9:5]: Echoed nonce, set by the state machine [4:0]: Selector The auto generation TX state machine generates the PRBS bit 49.
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UG-01143 2015.05.11 Register Definitions Word Addr Bit 0x4 C5 15:0 R/W RW Name User Next page low 2-189 Description The AN TX state machine uses these bits if the AN next pages ctrl bit is set. The following bits are defined: • • • • • [15]: Next page bit [14]: ACK, controlled by the state machine [13]: Message Page (MP) bit [12]: ACK2 bit [11]: Toggle bit For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
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2-190 UG-01143 2015.05.11 Register Definitions Word Addr Bit 24:0 R/W RO Name AN LP ADV Tech_ A[24:0] Description Received technology ability field bits of Clause 73 AutoNegotiation. The 10GBASE-KR PHY supports A0 and A2. The following protocols are defined: • • • • • • • A0 1000BASE-KX A1 10GBASE-KX4 A2 10GBASE-KR A3 40GBASE-KR4 A4 40GBASE-CR4 A5 100GBASE-CR10 A24:6 are reserved For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.
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UG-01143 2015.05.11 Register Definitions Word Addr 0x4 D0 Bit R/W Name 0 RW 1 RW dis_max_wait_tmr 2 RW quick_mode 3 RW pass_one 7:4 RW main_step_cnt [3:0] 11:8 RW prpo_step_cnt [3:0] Link Training enable Implementing Protocols in Arria 10 Transceivers Send Feedback 2-191 Description When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.
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2-192 UG-01143 2015.05.11 Register Definitions Word Addr Bit 14:12 R/W RW Name equal_cnt [2:0] Description Adds hysteresis to the error count to avoid local minimums. The following values are defined: • • • • • • • • 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 8 110 = 16 111 = Reserved The default value is 010. 15 RW 16 RW 17 RW 22 RW adp_ctle_mode Reserved.
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UG-01143 2015.05.11 Register Definitions Word Addr 0x4 D1 Bit R/W Name 0 RW 4 RW Updated TX Coef new 8 RW Updated RX coef new Restart Link training Implementing Protocols in Arria 10 Transceivers Send Feedback 2-193 Description When set to 1, resets the 10GBASE-KR start-up protocol. When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.
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2-194 UG-01143 2015.05.11 Register Definitions Word Addr 0x4 D2 Bit R/W 0 RO 1 RO 2 RO 3 RO 4 RO 5 RO 6 RO 7 RO Altera Corporation Name Link Trained Receiver status Link Training Frame lock Link Training Start-up protocol status Link Training failure Link Training Error Link Training Frame lock Error Description When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress.
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UG-01143 2015.05.11 Register Definitions Word Addr Bit 9:0 R/W RW Name ber_time_frames 2-195 Description Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames is 0. The following values are defined: • A value of 2 is about 103 bytes • A value of 20 is about 104 bytes • A value of 200 is about 105 bytes The default value for simulation is 2'b11. The default value for hardware is 0.
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2-196 UG-01143 2015.05.11 Register Definitions Word Addr Bit 5:0 R/W RO or RW Name LD coefficient update[5:0] Description Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writeable.
~~PAGE 228~~
UG-01143 2015.05.11 Register Definitions Word Addr Bit R/W 14 RO 21:16 RO or RW Name Link Training ready - LD Receiver ready LP coefficient update[5:0] 2-197 Description When set to 1, the local device receiver has determined that training is complete and it is prepared to receive data. When set to 0, the local device receiver requests that training continue. Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4.
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2-198 UG-01143 2015.05.11 Register Definitions Word Addr Bit R/W Name 23 RO or RW LP Preset Coefficients 29:24 RO LP coefficient status[5:0] Description When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit are defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2.
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UG-01143 2015.05.11 Register Definitions Word Addr 0x4 D5 Bit R/W Name 27:24 R RXEQ CTLE Setting 29:28 R RXEQ CTLE Mode 31:30 R RXEQ DFE Mode Implementing Protocols in Arria 10 Transceivers Send Feedback 2-199 Description Most recent ctle_rc setting sent to the reconfig bundle during RX equalization. Most recent ctle_mode setting sent to the reconfig bundle during RX equalization. Most recent dfe_mode setting sent to the reconfig bundle during RX equalization.
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2-200 UG-01143 2015.05.11 Register Definitions Word Addr Bit 4:0 R/W RW Name LT VODMAX ovrd Description Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only effects the local device TX output for the channel specified. This value must be greater than the INITMAINVAL parameter for proper operation. Note this will also override the PREMAINVAL parameter value.
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~~UG-01143 2015.05.11 Hard Transceiver PHY Registers Word Addr Bit R/W 0x4 D6 to 0x4 FF Name 2-201 Description Reserved for 40G KR Left empty for address compatibility with 40G MAC +PHY KR solution.~~
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2-202 UG-01143 2015.05.11 Arria 10 GMII PCS Registers Addr Bit Access Name Description 1 RO HI_BER 2 RO BLOCK_LOCK 3 RO TX_FIFO_FULL When set to 1, the TX_FIFO is full. 4 RO RX_FIFO_FULL When set to 1, the RX_FIFO is full. 7 RO Rx_DATA_READY 0x482 High BER status. When set to 1, the PCS reports a high BER. When set to 0, the PCS does not report a high BER. Block lock status. When set to 1, the PCS is locked to received blocks.
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UG-01143 2015.05.11 Arria 10 GMII PCS Registers Addr Bit R/W Name 2-203 Description 5 RW FD Full-duplex mode enable for the local device. Set to 1 for full-duplex support. 6 RW HD Half-duplex mode enable for the local device. Set to 1 for half-duplex support. This bit should always be set to 0 for the KR PHY IP. 8:7 RW PS2,PS1 Pause support for the local device.
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2-204 UG-01143 2015.05.11 Arria 10 GMII PCS Registers Addr Bit R/W Name 5 R FD 6 R HD 8:7 R PS2,PS1 0x495 (1000BA SE-X 13:1 R mode) 2 Description Full-duplex mode enable for the link partner. This bit must be 1 because only full duplex is supported. Half-duplex mode enable for the link partner. A value of 1 indicates support for half duplex. This bit must be 0 because half-duplex mode is not supported. Specifies pause support for link partner.
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2-206 UG-01143 2015.05.11 Arria 10 GMII PCS Registers Addr 0x496 Bit R/W 0 R 1 R Name LINK_PARTNER_AUTO_ NEGOTIATION_ABLE PAGE_RECEIVE Description Set to 1, indicates that the link partner supports AN. The default value is 0. A value of 1 indicates that a new page has been received with new partner ability available in the register partner ability. The default value is 0 when the system management agent performs a read access.
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UG-01143 2015.05.11 PMA Registers Addr 0x4A8 0x4A9 Bit R/W Name 2-207 Description 0 RW tx_invpolarity When set, the TX interface inverts the polarity of the TX data to the 8B/10B encoder. 1 RW rx_invpolarity When set, the RX channels inverts the polarity of the received data to the 8B/10B decoder. 2 RW rx_bitreversal_enable When set, enables bit reversal on the RX interface to the word aligner.
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2-208 UG-01143 2015.05.11 Speed Change Summary Address Bit R/W 0x466 0 RO 0x467 0 RO Name pma_rx_is_ lockedtodata pma_rx_is_ lockedtoref Description When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. When asserted, indicates that the RX CDR PLL is locked to the reference clock.
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UG-01143 2015.05.11 Design Guidelines 2-209 • ATX PLL on page 3-3 • Using the Altera Transceiver PHY Reset Controller on page 4-9 • 1G/10GbE PHY Functional Description on page 2-165 Design Guidelines Consider the following guidelines while designing with 1G/10GbE PHY. Using the 1G/10GbE PHY without the Sequencer The sequencer brings up channel-based initial datapath and performs parallel detection. To use the 1G/ 10GbE PHY without the sequencer, turn off the Enable automatic speed detection parameter.
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2-210 UG-01143 2015.05.11 Simulation Support default configuration includes two channels for backplane Ethernet and two channels for line-side (1G/ 10G) applications. Figure 2-62: 1G/10GbE PHY Only Design Example NF_DE_WRAPPER Test Harness Management Master ISSP Clock and Reset XGMII Test Harness Source XGMII Source JTAG-toAvalon-MM Master TH0_ADDR = 0xF nnn XGMII Sink XGMII Sink XGMII GEN XGMII GEN XGMII CHK XGMII CHK TH1_ADDR ... = 0xE nnn ...
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UG-01143 2015.05.11 TimeQuest Timing Constraints • • • • • • 2-211 ModelSim Verilog ModelSim VHDL VCS Verilog VCS VHDL NCSIM Verilog NCSIM VHDL simulation When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus II software optionally generates an IP functional simulation model. TimeQuest Timing Constraints To pass timing analysis, you must decouple the clocks in different time domains. The necessary Synopsys Design Constraints File (.
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UG-01143 2015.05.11 Transceiver Datapath in a XAUI Configuration 2-213 Figure 2-64: XAUI PHY IP Core XAUI PHY IP SDR XGMII 72 bits @ 156.25 Mbps Avalon-MM Control & Status XAUI PHY IP Core 4 PCS 8B/10B Word Aligner Phase Comp Hard PMA 4 4 x 3.125 Gbps serial Altera's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and Reduced XAUI (RXAUI) support is MorethanIP (MTIP). Related Information • IEEE 802.
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2-214 UG-01143 2015.05.11 XAUI Supported Features Figure 2-65: Transceiver Channel Datapath for XAUI Configuration The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.
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UG-01143 2015.05.11 XAUI Supported Features 2-215 Figure 2-66: Implementation of the XGMII Specification in Arria 10 Devices Configuration XGMII Transfer (DDR) Interface Clock (156.25 MHz) 8-bit Lane 0 D0 D1 D2 D3 Lane 1 D0 D1 D2 D3 Lane 2 D0 D1 D2 D3 Lane 3 D0 D1 D2 D3 Arria 10 Soft PCS Interface (SDR) Interface Clock (156.
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UG-01143 2015.05.11 2-217 XAUI PHY Device Family Support XAUI PHY Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. • Preliminary support—Verified with preliminary timing models for this device.
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2-218 UG-01143 2015.05.11 XAUI PHY Performance and Resource Utilization Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel. This ensures that the serial clock is running at 3.125 Gbps while the input reference clock is 156.25 MHz. Figure 2-68: Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled When phase compensation FIFO is enabled, you can connect the core to different clocks on the AvalonST interface.
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UG-01143 2015.05.11 XAUI PHY General Parameters 2-219 1. 2. 3. 4. For Which device family will you be using?, select Arria 10. Click Installed IP > Library > Interface Protocols > Ethernet > XAUI PHY. Use the tabs on the IP Catalog to select the options required for the protocol. Refer to the following topics to learn more about the parameters: a. General Parameters b. Analog Parameters c. Advanced Options Parameters 5. Click Finish to generate your customized XAUI PHY IP core.
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2-220 UG-01143 2015.05.11 XAUI PHY Ports Name Value Description Enable dynamic reconfiguration On / Off When you turn this option on, you can connect the dynamic reconfiguration ports to an external reconfiguration module. Enable rx_recovered_clk pin On / Off When you turn this option on, the RX recovered clock signal is an output signal. Enable phase compensation FIFO On / Off Enables the phase compensation FIFO to allow different clocks on the xgmii interface.
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UG-01143 2015.05.11 SDR XGMII TX Interface 2-221 Figure 2-70: Interleaved SDR XGMII Data Mapping Original XGMII Data [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [15:8] [39:32] [7:0] Interleaved Result [63:56] [31:24] [55:48] [23:16] [47:40] Related Information Avalon Interface Specifications SDR XGMII TX Interface Table 2-144: SDR TX XGMII Interface Signal Name xgmii_tx_dc[71:0] Direction Input Description Contains 4 lanes of data and control for XGMII.
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2-222 UG-01143 2015.05.11 Transceiver Serial Data Interface Signal Name Direction Input xgmii_rx_inclk Description The XGMII SDR RX input clock which runs at 156.25 MHz. This port is only available when Enable phase comensation FIFO is selected. Transceiver Serial Data Interface The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces. This interface runs at 3.125 Gbps. There is no separate clock signal because it is encoded in the data.
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UG-01143 2015.05.11 XAUI PHY Optional PMA Control and Status Interface Signal Name Direction 2-223 Description rx_ready Output Indicates PMA RX has exited the reset state and the transceiver can receive data. Synchronous to mgmt_clk. tx_ready Output Indicates PMA TX has exited the reset state and the transceiver can transmit data. Synchronous to mgmt_clk. pll_cal_busy_i Input Indicates the PLL calibration status.
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2-224 UG-01143 2015.05.11 XAUI PHY Register Interface and Register Descriptions XAUI PHY Register Interface and Register Descriptions The Avalon-MM PHY management interface provides access to the XAUI PHY IP core PCS, PMA, and transceiver reconfiguration registers. Table 2-150: Signals in the Avalon-MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input Avalon-MM clock input. phy_mgmt_clk_reset Input Global reset signal that resets the entire XAUI PHY.
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UG-01143 2015.05.11 XAUI PHY Register Interface and Register Descriptions Word Addr 0x042 Bits R/W Register Name 2-225 Description W reset_control(write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. This bit self-clears.
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2-226 UG-01143 2015.05.11 XAUI PHY Register Interface and Register Descriptions Word Addr Bits R/W Register Name 0x066 [31:0] RO pma_rx_is_lockedtodata 0x067 [31:0] RO pma_rx_is_lockedtoref Description When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit corresponds to channel . When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit corresponds to channel .
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UG-01143 2015.05.11 XAUI PHY TimeQuest SDC Constraint 2-227 Related Information Avalon Interface Specifications XAUI PHY TimeQuest SDC Constraint Refer to the "Timing Constraints for Bonded PCS and PMA Channels" section for the Synopsis Design Constraints (SDC) for XAUI. Related Information Timing Constraints for Bonded PCS and PMA Channels on page 4-20 Acronyms This table defines some commonly used Ethernet acronyms.
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2-228 UG-01143 2015.05.11 PCI Express (PIPE) PCI Express (PIPE) You can use Arria 10 transceivers to implement a complete PCI Express solution for Gen1, Gen2, and Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively. You can configure the transceivers for PCIe functionality using one of the following methods: • Arria 10 Hard IP for PCIe This is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers.
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~~2-230 UG-01143 2015.05.11 Gen1/Gen2 Features Table 2-154: Supported Features for PIPE Configurations Protocol Feature Gen1 Gen2 Gen3 (2.~~
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UG-01143 2015.05.11 Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) 2-231 configuration is based on the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate [1:0] that is function‐ ally equivalent to the RATE signal specified in the PCIe specification.
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2-232 Receiver Detection UG-01143 2015.05.11 Receiver Detection The PIPE interface block in Arria 10 transceivers provides an input signal pipe_tx_detectrx_loopback for the receiver detect operation. The PCIe protocol requires this signal to be high during the Detect state of the LTSSM. When the pipe_tx_detectrx_loopback signal is asserted in the P1 power state, the PIPE interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence.
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UG-01143 2015.05.11 2-233 Gen1 and Gen2 Clock Compensation Figure 2-74: Rate Match Deletion This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received. Skip Symbol Deleted First Skip Ordered Set Second Skip Ordered Set tx_parallel_data K28.5 K28.0 Dx.y K28.5 K28.0 rx_parallel_data K28.5 Dx.y K28.5 K28.0 K28.0 pipe_rx_status[2:0] 3’b010 xxx 3’b010 xxx xxx K28.0 K28.
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2-234 UG-01143 2015.05.11 PCIe Reverse Parallel Loopback Figure 2-77: Rate Match FIFO Empty The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become empty and drives pipe_rx_status[2:0] = 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after reading out data byte D3. tx_parallel_data D1 D2 D3 D4 D5 D6 rx_parallel_data D1 D2 D3 /K.30.
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UG-01143 2015.05.11 Gen3 Features 2-235 Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0 Gen3 Features The following subsections describes the Arria 10 transceiver block support for PIPE Gen3 features. The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control. Auto-Speed Negotiation PIPE Gen3 mode enables ASN between Gen1 (2.
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2-236 UG-01143 2015.05.11 Rate Switch PCIe Gen3 Capability Mode Enabled pipe_rate [1:0] Gen1 2'b00 Gen2 Gen3 2'b01 2'b1x Figure 2-79: Rate Switch Change The block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.
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UG-01143 2015.05.11 Gen3 Transmitter Electrical Idle Generation 2-237 Figure 2-80: Speed Change Sequence pipe_tx_elecidle pipe_rate[1:0] 00 10 pipe_sw[1:0] 00 10 pipe_sw_done[1:0] 00 10 pipe_phy_status Gen3 Transmitter Electrical Idle Generation In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during low power states. Before the transmitter enters electrical idle, you must send the Electrical Idle ordered set, consisting of 16 symbols with value 0x66.
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2-238 CDR Control UG-01143 2015.05.11 CDR Control The CDR control block performs the following functions: • Controls the PMA CDR to obtain bit and symbol alignment • Controls the PMA CDR to deskew within the allocated time • Generates status signals for other PCS blocks The PCIe base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates.
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UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2-239 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes Figure 2-83: Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode X1 Network 6 fPLL1 CGB Ch 5 CDR ATX PLL1 6 Master CGB1 CGB Ch 4 CDR 4 6 CGB Ch 3 CDR Path for Clocking in Gen1/Gen2 x1 Mode 6 CGB fPLL0 Ch 2 CDR Master CGB0 4 6 CGB Ch 1 CDR ATX PLL0 6 CGB Path for Clocking in Gen1/Gen2 x1 Mode Ch 0 CDR Notes: 1.
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2-240 UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes Figure 2-84: Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode XN Network X6 Network Ch 5 CGB 6 6 6 Connections Done via X1 Network CDR 6 Ch 4 CGB fPLL1 Master CGB CDR 6 Ch 3 CGB ATX PLL1 CDR Ch 2 CGB CDR Ch 1 CGB Master CGB CDR 6 Ch 0 CGB CDR Notes: 1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode. 2.
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UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2-241 Figure 2-85: Use ATX PLL or fPLL for Gen1/Gen2 x8 Mode CGB 6 6 6 CDR 6 CGB Master CGB Ch 5 Ch 4 CDR 6 CGB Ch 3 CDR Connections Done via X1 Network CGB fPLL1 Master CGB Use Any One PLL Transceiver bank CDR 6 CGB ATX PLL1 Ch 2 Ch 1 CDR CGB Ch 0 CDR CGB Ch 5 CDR CGB Master CGB 6 Ch 4 Transceiver bank CDR Notes: 1. Figure shown is just one possible combination for the PCIe Gen1/Gen2 x8 mode. 2.
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2-242 UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes Figure 2-86: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode X1 Network 6 fPLL1 CGB Ch 5 CDR ATX PLL1 6 Master CGB1 CGB Ch 4 CDR 4 6 CGB Ch 3 CDR 6 CGB fPLL0 Ch 2 CDR Master CGB0 4 6 CGB Ch 1 CDR ATX PLL0 6 CGB Ch 0 CDR Notes: 1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode. 2. Gen1/Gen2 modes use the fPLL only. 3. Gen3 mode uses the ATX PLL only. 4.
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UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2-243 Figure 2-87: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 Mode XN Network X6 Network CGB 6 6 6 Connections Done via X1 Network CDR 6 CGB fPLL1 Master CGB Ch 4 CDR 6 CGB ATX PLL1 Ch 5 Ch 3 CDR CGB Ch 2 CDR CGB Master CGB Ch 1 CDR 6 CGB Ch 0 CDR Notes: 1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x4 mode. 2.
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2-244 UG-01143 2015.05.11 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes Figure 2-88: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x8 Mode CGB 6 6 6 CDR 6 CGB Master CGB Ch 5 Ch 4 CDR 6 CGB Ch 3 CDR Connections Done via X1 Network CGB fPLL1 Master CGB Transceiver bank CDR 6 CGB ATX PLL1 Ch 2 Ch 1 CDR CGB Ch 0 CDR CGB Ch 5 CDR CGB Master CGB 6 Ch 4 Transceiver bank CDR Notes: 1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x8 mode. 2.
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UG-01143 2015.05.11 How to Implement PCI Express (PIPE) in Arria 10 Transceivers 2-245 How to Implement PCI Express (PIPE) in Arria 10 Transceivers Before you begin You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol. 1. Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core. Refer to Select and Instantiate the PHY IP Core on page 2-2 for more details. 2.
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for PIPE Gen1 PIPE Gen2 PIPE TX / RX Duplex TX / RX Duplex TX / RX Duplex Gen1 x1: 1 channel Gen2 x1: 1 channel Gen3 x1: 1 channel Gen1 x2: 2 channels Gen2 x2: 2 channels Gen3 x2: 2 channels Gen1 x4: 4 channels Gen2 x4: 4 channels Gen3 x4: 4 channels Gen1 x8: 8 channels Gen2 x8: 8 channels Gen3 x8: 8 channels Data rate 2.
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2-250 UG-01143 2015.05.11 Native PHY IP Parameter Settings for PIPE Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE Enable TX 8B/10B encoder Enabled Enabled Enabled Enable TX 8B/10B disparity control Enabled Enabled Enabled Enable RX 8B/10B decoder Enabled Enabled Enabled PIPE, PIPE 0ppm PIPE, PIPE 0ppm PIPE, PIPE 0ppm RX rate match insert / delete ve pattern (hex) 0x0002f17c (K28.5/ K28.0/) 0x0002f17c (K28.5/ K28.0/) 0x0002f17c (K28.5/K28.
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UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port tx_serial_clk0 / tx_ serial_clk1 Direction In Clock Domain N/A 2-255 Description The high speed serial clock generated by the PLL. Note: For Gen3 x1 ONLY tx_serial_ clk1 is used. pipe_hclk_in pipe_hclk_out In N/A Out N/A The 500 MHz clock used for the ASN block. This clock is generated by the PLL, configured for Gen1/Gen2. Note: For Gen3 designs, use from the fPLL that is used for Gen1/Gen2.
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2-256 UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port Direction Clock Domain Description For Gen3, indicates whether the 130bit block transmitted is a Data or Control Ordered Set Block. The following encodings are defined: 2'b10: Data block 2'b01: Control Ordered Set Block This value is read when pipe_tx_blk_ pipe_tx_sync_hdr[1:0] In tx_coreclkin start = 1b'1 Refer to Lane Level Encoding in the PCI Express Base Specification, Rev. 3.
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UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port pipe_tx_compliance Direction In Clock Domain tx_coreclkin 2-257 Description Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11 of Intel PHY Interface for PCI Express (PIPE) Architecture for more information. Active High pipe_rx_polarity In Asynchronous When 1'b1, instructs the PHY layer to invert the polarity on the received data.
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2-258 UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port pipe_tx_deemph Direction In Clock Domain Asynchronous Description Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis: 1'b0: –6 dB 1'b1: –3.5 dB For Gen3, selects the transmitter deemphasis.
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UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port Direction Clock Domain 2-259 Description The 2-bit encodings defined in the following list: pipe_rate[1:0] In Asynchronous 2'b00: Gen1 rate (2.5 Gbps) 2'b01: Gen2 rate (5.0 Gbps) 2'b1x: Gen3 rate (8.0 Gbps) pipe_sw_done pipe_tx_data_valid In In N/A tx_coreclkin Signal from the Master clock generation buffer, indicating that the rate switch has completed. Use this signal for bonding mode only.
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2-260 UG-01143 2015.05.11 Native PHY IP Ports for PIPE Port Direction Clock Domain Description For Gen3, indicates whether the 130bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined: 2'b10: Data block pipe_rx_sync_hdr[1:0] pipe_rx_blk_start Out Out 2'b01: Control Ordered Set block rx_coreclkin rx_coreclkin This value is read when pipe_rx_blk_ start = 4'b0001. Refer to Section 4.2.2.1.
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UG-01143 2015.05.11 How to Place Channels for PIPE Configurations Port Direction Clock Domain 2-261 Description Signal encodes receive status and error codes for the receive data stream and receiver detection.
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2-262 UG-01143 2015.05.11 Master Channel in Bonded Configurations Note: Whichever channel you pick as the PCS master, the fitter will select physical CH1 or CH4 of a transceiver bank as the master channel. This is because the ASN and Master CGB connectivity only exists in the hardware of these two channels of the transceiver bank.
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UG-01143 2015.05.11 Master Channel in Bonded Configurations 2-263 Figure 2-92: x4 Configuration The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master Channel number must be specified as channel 1.
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2-264 UG-01143 2015.05.11 Master Channel in Bonded Configurations Figure 2-93: x8 Configuration For x8 configurations, Altera recommends you choose a master channel that is a maximum of four channels away from the farthest slave channel.
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UG-01143 2015.05.11 PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate 2-265 Figure 2-94: x4 Alternate Configuration The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master Channel number must be specified as channel 4.
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2-266 UG-01143 2015.05.11 PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate Phase 0 Phase 0 includes the following steps: 1. The upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s. 2. The downstream component enters Phase 0 of equalization after exiting Recovery.Speed at 8 GT/s.
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UG-01143 2015.05.11 Design Example 2-267 Where: C0 is the main cursor (boost), C-1 is the pre-cursor (pre-shoot), and C+1 is the post-cursor (deemphasis). 3. This process is repeated until the downstream component's receiver achieves a BER of < 10-12 Phase 3 (Optional) During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2 but operates in the opposite direction.
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2-268 UG-01143 2015.05.11 CPRI CPRI The common public radio interface (CPRI) is a high-speed serial interface developed for wireless network radio equipment controller (REC) to uplink and downlink data from available remote radio equipment (RE). The CPRI protocol defines the interface of radio base stations between the REC and the RE.
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UG-01143 2015.05.11 TX PLL Selection for CPRI 2-269 Table 2-164: Channel Width Options for Supported Serial Data Rates Channel Width (FPGA-PCS Fabric) Serial Data Rate (Mbps) 8/10 Bit Width 16/20 Bit Width 8-Bit 16-Bit 16-Bit 32-Bit 614.4 Yes Yes N/A N/A 1228.8 Yes Yes Yes Yes 2457.6 Yes Yes Yes Yes 3072 Yes Yes Yes Yes 4915.2 N/A N/A Yes Yes 6144 N/A N/A Yes Yes 9830.
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2-270 UG-01143 2015.05.11 Supported Features for CPRI Data Rate (Mbps) Base Data Rate Local CGB Divider 3072.0 6144.0 2 4915.2 9830.4 2 6144.0 6144.0 1 9830.4 9830.4 1 Supported Features for CPRI The CPRI protocol places stringent requirements on the amount of latency variation that is permissible through a link that implements these protocols. CPRI (Auto) and CPRI (Manual) transceiver configuration rules are both available for CPRI designs.
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UG-01143 2015.05.11 How to Implement CPRI in Arria 10 Transceivers 2-273 Refer to Select and Instantiate the PHY IP Core on page 2-2 for more details. 2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing. 3. Use the parameter values in the tables in Native PHY IP Parameter Settings for CPRI on page 2-275 as a starting point. Or, you can use the protocol presets described in Presets.
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UG-01143 2015.05.11 Native PHY IP Parameter Settings for CPRI 2-275 Native PHY IP Parameter Settings for CPRI Table 2-168: General and Datapath Options The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
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UG-01143 2015.05.11 Other Protocols Parameter 2-279 Value Generate C header file Off Generate MIF (Memory Intialization File) Off Table 2-173: Generation Options Parameter Generate parameter documentation file Value On Other Protocols Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G or 10G-like protocols.
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2-280 UG-01143 2015.05.11 Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations... Figure 2-101: Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) Configuration FPGA Fabric Enhanced PCS TX FIFO Interlaken Frame Generator 32-bit data PRP Generator tx_clkout Transcode Encoder KR FEC Encoder KR FEC TX Gearbox KR FEC Scrambler Parallel Clock (322.265625 MHz) 322.
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~~UG-01143 2015.05.11 2-281 How to Implement the Basic (Enhanced PCS) and Basic with KR FEC...~~
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~~2-282 UG-01143 2015.05.11 How to Implement the Basic (Enhanced PCS) and Basic with KR FEC...~~
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UG-01143 2015.05.11 How to Implement the Basic (Enhanced PCS) and Basic with KR FEC... 2-283 Figure 2-104: Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design PLL IP Design Testbench Reset Controller 32-bit data (32:32 gearbox ratio) Arria 10 Transceiver Native PHY Figure 2-105: Connection Guidelines for a Basic with KR FEC Transceiver Design PLL IP Reset Controller Design Testbench 64d + 8c Arria 10 Transceiver Native PHY 8. Simulate your design to verify its functionality.
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2-284 UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic... Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC Table 2-174: General and Datapath Parameters The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver.
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~~UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic...~~
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~~2-286 UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic...~~
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~~UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic...~~
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UG-01143 2015.05.11 TX Bit Slip 2-289 Double-width mode: 40:40, 64:64, or 66:64 3. Select Phase_compensation in the TX and RX FIFO mode list. 4. If you need the Scrambler and Descrambler features, enable Block Synchronize and use the 66:32, 66:40, or 66:64 gear ratio. TX Bit Slip The bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the serializer. The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI.
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2-290 UG-01143 2015.05.11 RX Polarity Inversion Figure 2-107: RX Bit Slip rx_clkout rx_bitslip rx_parallel_data[63:0] 64’d0 64’d1 RX Polarity Inversion Use the RX polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable RX polarity inversion, select the Enable RX data polarity inversion option in the Gearbox section of Qsys. It can also be dynamically controlled with dynamic reconfiguration.
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UG-01143 2015.05.11 2-291 Using the Basic/Custom, Basic/Custom with Rate Match Configurations of... Figure 2-108: Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate Match Configurations The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
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2-292 UG-01143 2015.05.11 Word Aligner Manual Mode Figure 2-109: Transceiver Channel Datapath and Clocking for Basic Configuration with Low Latency Enabled The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits. Transmitter Standard PCS Transmitter PMA 16 TX FIFO Byte Serializer 8B/10B Encoder TX Bit Slip Serializer tx_serial_data 10 FPGA Fabric PRBS Generator 625 MHz (2) tx_coreclkin tx_clkout 125 MHz (1) 62.
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UG-01143 2015.05.11 Word Aligner Manual Mode 2-293 This mode adds rx_patterndetect and rx_syncstatus. You can select the Enable rx_std_wa_patterna‐ lign port option to enable rx_std_wa_patternalign. An active high on rx_std_wa_patternalign realigns the word aligner one time. Note: • • • • rx_patterndetect is asserted whenever there is a pattern match. rx_syncstatus is asserted after the word aligner achieves synchronization. rx_std_wa_patternalign is asserted to re-align and resynchronize.
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~~2-296 UG-01143 2015.05.11 RX Bit Slip You can verify this feature by monitoring rx_parallel_data.~~
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2-298 UG-01143 2015.05.11 RX Byte Reversal a bus in which each bit corresponds to a channel. As long as rx_std_bitrev_ena is asserted, the RX data received by the core shows bit reversal. You can verify this feature by monitoring rx_parallel_data.
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UG-01143 2015.05.11 Rate Match FIFO in Basic (Single Width) Mode Parameter Value 2-299 Description RX rate match insert/delete –ve 20 bits of data The first 10 bits correspond to the skip pattern pattern (hex) specified as a hexadec‐ and the last 10 bits correspond to the control imal string pattern. The skip pattern must have neutral disparity. ve (volt encodes) are NRZ_L conditions where +ve encodes 0 and –ve encodes 1. ve is a running disparity (+/–RD) specifically used with the rate matcher.
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2-300 UG-01143 2015.05.11 Rate Match FIFO Basic (Double Width) Mode Figure 2-123: Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion First Skip Cluster Second Skip Cluster tx_parallel_data K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 Dx.y rx_parallel_data K28.5 K28.0 K28.0 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 K28.0 Dx.
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UG-01143 2015.05.11 2-301 Rate Match FIFO Basic (Double Width) Mode Parameter Value RX rate match insert/delete -ve pattern (hex) Description 20 bits of data The first 10 bits correspond to the skip specified as a pattern and the last 10 bits correspond hexadecimal string to the control pattern. The skip pattern must have neutral disparity. The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing.
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2-302 UG-01143 2015.05.11 8B/10B Encoder and Decoder Figure 2-127: Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion First Skip Cluster Second Skip Cluster tx_parallel_data[19:10] Dx.y K28.0 Dx.y K28.5 K28.0 K28.0 tx_parallel_data[9:0] Dx.y K28.5 Dx.y Dx.y K28.0 K28.0 rx_parallel_data[19:0] Dx.y K28.0 K28.0 K28.0 Dx.y K28.5 K28.0 K28.0 rx_parallel_data[9:0] Dx.y K28.5 K28.0 K28.0 Dx.y Dx.y K28.0 K28.
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UG-01143 2015.05.11 8B/10B TX Disparity Control 2-303 The following ports are added: • • • • • tx_datak rx_datak rx_runningdisp rx_disperr rx_errdetect rx_datak and tx_datak indicate whether the parallel data is a control word or a data word. The incoming 8-bit data (tx_parallel_data) and the control identifier (tx_datak) are converted into a 10-bit data. After a power on reset, the 8B/10B encoder takes the 10-bit data from the RD- column.
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2-304 UG-01143 2015.05.11 TX Bit Slip 6. Ensure that RX rate match FIFO mode is disabled. 7. Set the RX word aligner mode to bitslip. 8. Set the RX word aligner pattern length to 7 or 16. Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are supported. TX Bit Slip To use the TX bit slip, select the Enable TX bitslip and Enable tx_std_bitslipboundarysel port options. This adds the tx_std_bitslipboundarysel input port.
~~PAGE 336~~
UG-01143 2015.05.11 TX Polarity Inversion 2-305 Figure 2-133: TX Bit Slip in 20-bit Mode tx_parallel_data = 20'hF3CBC. tx_std_bitslipboundarysel = 5'b00111 (bit slip by 7 bits). tx_std_bitslipboundarysel 00111 tx_parallel_data f3cbc rx_parallel_data e5e1f TX Polarity Inversion The positive and negative signals of a serial differential link might accidentally be swapped during board layout. Solutions such as a board respin or major updates to the PLD logic can be expensive.
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2-306 How to Implement the Basic, Basic with Rate Match Transceiver... UG-01143 2015.05.11 How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria 10 Transceivers Before you begin You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your Basic protocol IP. 1. Open the IP Catalog and select the Native PHY IP. Refer to Select and Instantiate the PHY IP Core on page 2-2. 2.
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~~UG-01143 2015.05.11 How to Implement the Basic, Basic with Rate Match Transceiver...~~
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~~2-308 UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic, Basic with Rate Match...~~
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~~UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic, Basic with Rate Match...~~
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~~2-310 UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic, Basic with Rate Match...~~
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~~UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic, Basic with Rate Match...~~
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~~2-312 UG-01143 2015.05.11 Native PHY IP Parameter Settings for Basic, Basic with Rate Match...~~
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UG-01143 2015.05.11 2-313 Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT... Table 2-184: Dynamic Reconfiguration Parameters Parameter Range Enable dynamic reconfiguration On/Off Share reconfiguration interface On/Off Enable Altera Debug Master Endpoint On/Off Table 2-185: Generation Options Parameters Parameter Range Generate parameter documentation file On/Off Design Considerations for Data Rates Above 17.
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2-314 UG-01143 2015.05.11 Transceiver PHY IP Notes on grouping channels Ch0, Ch1, and Ch2: • If channels 0 and 1 are configured as GT channels, channel 2 is unusable. • If either channel 0 or 1 is configured as a GT channel, only one other channel can be used in this grouping. • If channels 0 and 1 are not configured as GT channels, this grouping can be all configured as GX channels.
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UG-01143 2015.05.11 PLL and GT Transceiver Channel Clock Lines 2-315 Figure 2-138: GT Channel Configuration CGB Ch 5 CDR CGB Ch 4 CMU or CDR ATX PLL1 CGB Ch 3 CDR CGB Ch 2 CDR CGB ATX PLL0 Ch 1 CMU or CDR CGB Ch 0 CDR When both the channels 0 and 1 are configured as GT channels, they are driven by the same ATX PLL and have to be configured to run at the same data rates. This is also true for channels 3 and 4 when they are configured as GT channels.
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2-316 UG-01143 2015.05.11 Reset Controller Reset Controller Each GT channel instantiated will have independent analog and digital reset ports. Refer to the Resetting Transceiver Channels chapter for more details on designing a reset controller to reset these ports.
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~~UG-01143 2015.05.11 Native PHY IP Parameter Settings for PCS Direct Transceiver...~~
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~~2-318 UG-01143 2015.05.11 Native PHY IP Parameter Settings for PCS Direct Transceiver...~~
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~~UG-01143 2015.05.11 How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced...~~
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2-320 UG-01143 2015.05.11 How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced... as a starting point. Or, you can use the protocol presets described in Presets. You can then modify the settings to meet your specific requirements. • Ensure that the data rate is between 17400 and 28100 Mbps. Select a CDR reference clock to match your data rate. • Set the Enhanced PCS / PMA interface width to 64 bits. • Set the FPGA Fabric / Enhanced PCS interface width to 64 bits.
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UG-01143 2015.05.11 How to Implement PCS Direct Transceiver Configuration Rule 2-321 Figure 2-141: ATX PLL IP with GT Clock Lines Enabled 6. Create a transceiver reset controller. Refer to Resetting Transceiver Channels on page 4-1 for more details about configuring the reset IP. 7. Connect the Native PHY IP to the PLL IP and the reset controller. The ATX PLL's port tx_serial_clk_gt represents the dedicated GT clock lines. Connect this port to the Native PHY IP's tx_serial_clk0 port.
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2-322 UG-01143 2015.05.11 Simulating the Transceiver Native PHY IP Core 5. Instantiate and configure your PLL. 6. Create a transceiver reset controller. You can use your own controller or use the Altera Transceiver PHY Reset Controller IP. 7. Connect the Native PHY IP to the PLL IP and the reset controller.
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UG-01143 2015.05.11 NativeLink Simulation Flow 2-323 You can simulate the following netlist: • The RTL functional netlist—This netlist provides cycle-accurate simulation using Verilog HDL, SystemVerilog, and VHDL design source code. Altera and third-party EDA vendors provide the simulation models. Prerequisites to Simulation Before you can simulate your design, you must have successfully passed Quartus II Analysis and Synthesis.
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2-324 How to Use NativeLink to Specify a ModelSim-Altera Simulation c. d. e. f. g. h. Altera Corporation UG-01143 2015.05.11 The Test Benches dialog box appears. Click New. Under Create new test bench settings, for Test bench name type the test bench name. For Top level module in the test bench, type the top-level module name. These names should match the actual test bench module names.
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2-326 UG-01143 2015.05.11 How to Use NativeLink to Specify Third-Party RTL Simulators 4. 5. 6. 7. of the device. Consequently, you must route any signal that you want to observe to the top-level of your design. To monitor additional signals, highlight the desired instances or nodes in Instance, and right-click Add wave. Select Simulate and then Run. Specify the simulation duration. Complete the following steps to restart the simulation: a.
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~~UG-01143 2015.05.~~
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2-328 UG-01143 2015.05.11 Custom Simulation Flow Table 2-195: Simulator Path Simulator Mentor Graphics ModelSim Mentor Graphics QuestaSim Path :\\win32 (Windows) //bin (Linux) Synopsys VCS/VCS MX //bin (Linux) Cadence Incisive Enterprise //tools/bin (Linux) Aldec Active-HDL :\\bin (Windows) Aldec Riviera-Pro //bin (Linux) 3. 4. 5. 6.
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2-330 UG-01143 2015.05.11 How to Generate Scripts Complete the following steps to compile the simulation model libraries using the Simulation Library Compiler: 1. On the Tools menu, click Launch Simulation Library Compiler. 2. Under EDA simulation tool, for the Tool name, select your simulation tool. 3. Under Executable location, browse to the location of the simulation tool you specified. You must specify this location before you can run the EDA Simulation Library Compiler. 4.
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UG-01143 2015.05.11 Qsys Simulation Scripts Simulator Aldec Riviera Pro Simulation File /simulation/ aldec/rivierapro_ setup.tcl 2-331 Use Source directly with your simulator . Synopsys VCS /simulation/synopsys/vcs/vcs_ setup.sh Add your testbench file name to this file to pass the testbench file to VCS using the –file option. If you specify a testbench file for NativeLink and do not choose to simulate, NativeLink generates a script that runs VCS.
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2-332 Use the ip-make-simscript Utility UG-01143 2015.05.11 This utility compiles IP simulation models into simulation libraries. Complete the following steps to use this command in Qsys: 1. On the Qsys Tools menu, select Nios II Command Shell [gcc4]. A command shell appears. 2. To get usage information for the ip-make-simscript utility, type the following command: ip-make-simscript --help 3. Type ip-make-simscript with the appropriate arguments. 4.
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PLLs and Clock Networks 3 2015.05.11 UG-01143 Subscribe Send Feedback This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the clocking options for the transceiver and the FPGA fabric interface. As shown in the following figure, transceiver banks can have either three or six transceiver channels. For every three channels, you get one advanced transmit (ATX) PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB).
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~~3-2 UG-01143 2015.05.~~
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UG-01143 2015.05.11 PLLs 3-3 • Channel Bonding on page 3-44 PLLs Table 3-1: Transmit PLLs in Arria 10 Devices PLL Type Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Clock Multiplier Unit (CMU) PLL or Channel PLL (45) Data Rate Range Characteristics 611 Mbps to 28.3 Gbps(44) • Best jitter performance • LC tank based voltage controlled oscillator (VCO) • Supports fractional synthesis mode • Used for both bonded and nonbonded channel configurations 611 Mbps to 12.
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3-4 UG-01143 2015.05.11 ATX PLL Figure 3-2: ATX PLL Block Diagram Lock Detector pll_locked 2 VCO 1 CP & LF VCO 2 L Counter VCO 3 Refclk Multiplexer Dedicated reference clock pin Reference clock network Receiver input pin Output of another PLL with PLL cascading Global clock or core clock 2 Input reference clock /2 Up N Counter refclk Down PFD fbclk M Counter Delta Sigma Modulator (1) Note: (1) The Delta Sigma Modulator is enaged only when the ATX PLL is used in fractional mode.
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UG-01143 2015.05.11 Instantiating the ATX PLL IP Core 3-5 signal at the output of the N counter to the feedback clock (fbclk) signal. The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.
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3-6 UG-01143 2015.05.11 ATX PLL IP Core 1. Open the Quartus II software. 2. Click Tools > IP Catalog. 3. In IP Catalog, under Library > Transceiver PLL > , select Arria 10 Transceiver ATX PLL and click Add. 4. In the New IP Instance dialog box, provide the IP instance name. 5. Select the Arria 10 device family. 6. Select the appropriate device and click OK. The ATX PLL IP core Parameter Editor window opens.
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UG-01143 2015.05.11 ATX PLL IP Core Parameter Primary PLL clock output buffer Enable PLL GX clock output port (46) Range 3-7 Description GX clock output Specifies which PLL output is active initially. buffer • If GX is selected, turn ON "Enable PLL GX GT clock output clock output port". buffer • If GT is selected, turn ON “Enable PLL GT clock output port". Cascade Source • If Cascade Source is selected, turn ON "Enable ATX to FPLL cascade clock output port".
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3-8 UG-01143 2015.05.11 ATX PLL IP Core Parameter PLL integer reference clock frequency Range User-defined Description Specifies the reference clock frequency for the ATX PLL in fractional mode. This parameter is only applicable for the ATX PLL in fractional mode. When you enable the fractional mode for ATX PLL, this parameter replaces the PLL reference clock frequency parameter in the Parameter Editor window. Multiply factor (M-Counter) Read only Displays the M-counter value.
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UG-01143 2015.05.11 ATX PLL IP Core Parameter Range Enable bonding clock output ports On/Off 3-9 Description Enables the tx_bonding_clocks output ports of the master CGB used for channel bonding. This option should be turned ON for bonded designs. Enable feedback compensation bonding PMA interface width On/Off Enables this setting when using feedback compensa‐ tion bonding.
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3-10 UG-01143 2015.05.11 ATX PLL IP Core Parameter Range Description Generate SystemVerilog package file On/Off Generates a SystemVerilog package file containing all relevant parameters used by the PLL. Generate C header file On/Off Generates a C header file containing all relevant parameters used by the PLL. Generate MIF (Memory Initialize File) On/Off Generates a MIF file which contains the current configuration.
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UG-01143 2015.05.11 ATX PLL IP Core Port 3-11 Direction Clock Domain Description pll_locked Output Asynchronous pll_pcie_clk Output N/A Used for PCIe. (49) reconfig_clk0 Input N/A Optional Avalon interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the Enable Reconfigura‐ tion parameter is selected in the PLL IP GUI. When this parameter is not selected, the ports are set to OFF internally.
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3-12 UG-01143 2015.05.11 ATX PLL IP Core Port mcgb_rst Direction Clock Domain Input Asynchronous Description Master CGB reset control. If you use PLL feedback compensation bonding mode, deassert this reset at the same time as pll_powerdown . If you do not use PLL feedback compensation bonding, then you can deassert this port after pll_ powerdown is deasserted, but before tx_analogreset is deasserted. Alternatively, you can deassert this port at the same time as pll_powerdown .
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UG-01143 2015.05.11 fPLL 3-13 fPLL The fractional PLL (fPLL) is used for generating lower clock frequencies. It supports both integer and fractional frequency synthesis. The fPLL can be used as a transmit PLL for transceiver applications. The fPLL can be cascaded to the ATX or to another fPLL, or it can be used to drive the FPGA core clock network. A single fPLL can be used in only one of these applications at a time. Simultaneous operations are not supported.
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3-14 UG-01143 2015.05.11 fPLL Reference Clock Multiplexer The refclk mux selects the reference clock to the PLL from the various available reference clock sources. N Counter The N counter divides the reference clock (refclk) mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency within the phase frequency detector's (PFD) operating range. The N counter supports division factors from 1 to 32.
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UG-01143 2015.05.11 Instantiating the fPLL IP Core 3-15 Dynamic Phase Shift The dynamic phase shift block allows you to adjust the phase of the M and C counters in user mode. In fractional mode, dynamic phase shift is only available for the C counters. Adjusting the M counter may cause the fPLL to lose lock. Latency The fPLL contains a 1 ns delay with 50 ps resolution on each C, M, and N counter. In addition, there is a 7 ns delay with 1 ns resolution on both the reference clock and feedback clock paths.
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3-16 UG-01143 2015.05.11 fPLL IP Core Parameters Enable fractional mode Range On/Off Description Enables the fractional frequency mode. This enables the PLL to output frequencies which are not integral multiples of the input reference clock. Enable manual counter configurations On/Off Selecting this option allows you to manually specify M, N, C and L counter values. Enable cascade input port On/Off Enables the ATX to fPLL cascade clock input port.
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UG-01143 2015.05.11 fPLL IP Core 3-17 Table 3-8: fPLL—Master Clock Generation Block Parameters and Settings Parameters Include Master Clock Generation Block Range On/Off Description When enabled, includes a master CGB as a part of the fPLL IP core. The PLL output drives the master CGB. This is used for x6/xN bonded and non-bonded modes. Clock division factor 1, 2, 4, 8 Divides the master CGB clock input before generating bonding clocks.
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3-18 UG-01143 2015.05.11 fPLL IP Core Parameter Range Enable Altera Debug Master Endpoint On/Off When you turn this option ON, the transceiver PLL IP core includes an embedded Altera Debug Master Endpoint (ADME) that connects internally to the Avalon-MM slave interface for dynamic reconfigu‐ ration. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
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UG-01143 2015.05.11 fPLL IP Core Port pll_refclk0 Range Clock Domain input N/A 3-19 Description Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter. pll_refclk1 input N/A Reference clock input port 1. pll_refclk2 input N/A Reference clock input port 2. pll_refclk3 input N/A Reference clock input port 3. pll_refclk4 input N/A Reference clock input port 4.
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3-20 UG-01143 2015.05.11 fPLL IP Core Port Range Clock Domain reconfig_readdata0[31:0] output reconfig_clk0 reconfig_waitrequest0 output reconfig_clk0 pll_cal_busy output Asynchronous Description 32-bit data bus. Carries the read data from the specified address. Indicates when the Avalon interface signal is busy. When asserted, all inputs must be held constant. Status signal which is asserted high when PLL calibration is in progress.
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UG-01143 2015.05.11 CMU PLL Port 3-21 Range Clock Domain input Asynchronous 2-bit rate switch control input used for PCIe protocol implementation. output Asynchronous 2-bit rate switch status output used for PCIe protocol implementation. atx_to_fpll_cascade_clk input N/A Enables fPLL to ATX PLL cascading clock output port.
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3-22 UG-01143 2015.05.11 CMU PLL Figure 3-4: CMU PLL Block Diagram User Control (LTR/LTD) Lock to Reference Controller CP + LF Refclk Multiplexer Reference clock network Input reference clock Receiver input pin N Counter Lock to Reference Lock Detector refclk Up VCO PLL Lock Status L Counter Output Down PFD fbclk M Counter VCO Calibration Input Reference Clock The input reference clock for a CMU PLL can be sourced from either the reference clock network or a receiver input pin.
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UG-01143 2015.05.11 Instantiating CMU PLL IP Core 3-23 The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage which drives the VCO frequency. Voltage Controlled Oscillator (VCO) The CMU PLL has a ring oscillator based VCO. The fundamental VCO frequency range is from 4 GHz to 14 GHz.
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3-24 UG-01143 2015.05.11 CMU PLL IP Core CMU PLL IP Core Table 3-12: CMU PLL Parameters and Settings Parameters Message level for rule violations Range Error Warning Bandwidth Low Medium High Number of PLL reference clocks 1 to 5 Description Specifies the messaging level to use for parameter rule violations. • Error - Causes all rule violations to prevent IP generation. • Warning - Displays all rule violations as warnings and will allow IP generation in spite of violations.
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UG-01143 2015.05.11 CMU PLL IP Core 3-25 Table 3-13: CMU PLL—Dynamic Reconfiguration Parameters Range Enable dynamic reconfigura‐ tion On/Off Enables the PLL reconfiguration interface. Enables the simulation models and adds more ports for reconfiguration. Enable Altera Debug Master Endpoint On/Off When you turn this option On, the transceiver PLL IP includes an embedded Altera Debug Master Endpoint that connects internally to the AvalonMM slave interface for dynamic reconfiguration.
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3-26 UG-01143 2015.05.11 CMU PLL IP Core Table 3-15: CMU PLL IP Ports Port Range Clock Domain Description pll_powerdown input Asynchronous Resets the PLL when asserted high. pll_refclk0 input N/A Reference clock input port 0. There are 5 reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter. pll_refclk1 input N/A Reference clock input port 1. pll_refclk2 input N/A Reference clock input port 2.
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UG-01143 2015.05.11 Input Reference Clock Sources Port Range Clock Domain reconfig_address0[9:0] input reconfig_clk0 reconfig_writedata0[31:0] input reconfig_clk0 reconfig_readdata0[31:0] output reconfig_clk0 reconfig_waitrequest0 output reconfig_clk0 pll_cal_busy output Asynchronous 3-27 Description 10-bit address bus used to specify address to be accessed for both read and write operations. 32-bit data bus. Carries the write data to the specified address. 32-bit data bus.
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~~3-28 UG-01143 2015.05.11 Dedicated Reference Clock Pins Altera recommends using the dedicated reference clock pins and the reference clock network for the best jitter performance.~~
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UG-01143 2015.05.11 Receiver Input Pins 3-29 Figure 3-6: Dedicated Reference Clock Pins There are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk pin feeds the bottom ATX PLL, fPLL and CMU PLL. The top refclk pin feeds the top ATX PLL, fPLL and CMU PLL. The dedicated reference clock pins can also drive the reference clock network.
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3-30 UG-01143 2015.05.11 PLL Cascading as an Input Reference Clock Source The receiver input pin drives the reference clock network, which can then feed any number of transmitter PLLs on the same side of the device. When a receiver input pin is used as an input reference clock source, the clock data recovery (CDR) block of that channel is not available. As indicated in Figure 3-5, only one RX differential pin pair per three channels can be used as an input reference clock source at any given time.
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UG-01143 2015.05.11 x1 Clock Lines 3-31 x1 Clock Lines The x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiver bank. The low speed parallel clock is then generated by that particular channel's local clock generation block (CGB). Non-bonded channel configurations use the x1 clock network. The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank.
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3-32 UG-01143 2015.05.11 x6 Clock Lines Figure 3-7: x1 Clock Lines x1 Network CGB Ch 5 fPLL1 Master CGB CDR CGB ATX PLL1 Ch 4 CMU or CDR CGB Ch 3 CDR CGB fPLL0 Ch 2 CDR Master CGB CGB Ch 1 CMU or CDR ATX PLL0 CGB Ch 0 CDR x6 Clock Lines The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are driven by the master CGB. There are two x6 clock lines per transceiver bank, one for each master CGB.
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UG-01143 2015.05.11 xN Clock Lines 3-33 The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiver banks. Figure 3-8: x6 Clock Lines x6 Network x6 Top x6 Bottom CGB Ch 5 CDR CGB Ch 4 CMU or CDR Master CGB CGB Ch 3 CDR CGB Ch 2 CDR CGB Ch 1 CMU or CDR Master CGB CGB Ch 0 CDR xN Clock Lines The xN clock lines route the transceiver clocks across multiple transceiver banks.
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3-34 UG-01143 2015.05.11 xN Clock Lines configurations, the low speed parallel clock output of the master CGB is used, and the local CGB within each channel is bypassed. For non-bonded configurations, the master CGB provides a high speed serial clock output to each channel.
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UG-01143 2015.05.11 GT Clock Lines 3-35 a bonded group must share the same voltage. The data rates supported by different transceiver voltage levels are pending characterization. Related Information • Implementing x6/xN Bonding Mode on page 3-54 • x6/xN Bonding on page 3-44 GT Clock Lines GT clock lines are dedicated clock lines available only in Arria 10 GT devices. Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the transceiver channels within a transceiver bank.
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~~3-36 UG-01143 2015.05.~~
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UG-01143 2015.05.11 Clock Generation Block 3-37 Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configura‐ tions, the serial clock generated by the transmit PLL drives the local CGB of each channel. The local CGB generates the parallel clock used by the serializer and the PCS. There are two standalone master CGBs within each transceiver bank. The master CGB provides the same functionality as the local CGB within each transceiver channel.
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3-38 UG-01143 2015.05.11 Clock Generation Block Figure 3-11: Clock Generation Block and Clock Network The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network, or the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the ATX PLL 1 drives the x1 network which in turn drives the master CGB. The master CGB then drives the x6 clock network which routes the clocks to the local channels.
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UG-01143 2015.05.11 FPGA Fabric-Transceiver Interface Clocking 3-39 FPGA Fabric-Transceiver Interface Clocking The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks in the FPGA core.
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~~3-40 UG-01143 2015.05.~~
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UG-01143 2015.05.11 3-41 Transmitter Data Path Interface Clocking Note: Refer to the "TX PMA Optional Ports" table in PMA Parameters section for details about selecting the division factor. These clocks can be used to meet core timing by operating the TX and RX FIFO in double-width mode, as this halves the required clock frequency at the PCS to/from FPGA interface. These clocks can also be used to clock the core side of the TX and RX FIFOs when the Enhanced PCS Gearbox is used.
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3-42 UG-01143 2015.05.11 Receiver Data Path Interface Clocking If you choose to use a different clock than the tx_clkout to clock the write side of the phase compensa‐ tion FIFO, then you must ensure that the clock provided has a 0 ppm frequency difference with respect to the tx_clkout. Figure 3-14: Transmitter Enhanced PCS and PMA Clocking The master or local CGB provides the serial clock to the serializer of the transmitter PMA, and the parallel clock to the transmitter PCS.
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UG-01143 2015.05.11 3-43 Receiver Data Path Interface Clocking For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the byte deserializer and the write side of the RX phase compensation FIFO.
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3-44 Channel Bonding UG-01143 2015.05.11 You can clock the receiver datapath interface using one of the following methods: • Quartus II selected receiver datapath interface clock • User-selected receiver datapath interface clock Channel Bonding For Arria 10 devices, two types of bonding modes are available: • PMA bonding • PMA and PCS bonding Note: Channel bonding is not supported by GT channels. PMA Bonding PMA bonding reduces skew between PMA channels.
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UG-01143 2015.05.11 PLL Feedback Compensation Bonding 3-45 PLL Feedback Compensation Bonding In PLL feedback compensation bonding, channels are divided into bonded groups based on physical location with a three-channel or six-channel transceiver bank. All channels within the same six-channel transceiver bank are assigned to the same bonded group. In PLL feedback compensation bonding, each bonded group is driven by its own set of high-speed serial and low-speed parallel clocks.
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3-46 UG-01143 2015.05.11 PMA and PCS Bonding For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For PCS bonding, some of the PCS control signals within the bonded group are skew aligned using dedicated hardware inside the PCS.
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UG-01143 2015.05.11 Selecting Channel Bonding Schemes 3-47 Selecting Channel Bonding Schemes In Arria 10 devices, select PMA and PCS bonding for bonded protocols that are explicitly supported by the hard PCS blocks. For example, PCI-Express, SFI-S, and 40GBASE-KR. Select PMA-only bonding when a bonded protocol is not explicitly supported by the hard PCS blocks. For example, for Interlaken protocol, PMA-only bonding is used and a soft PCS bonding IP is implemented in the FPGA fabric.
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~~3-48 UG-01143 2015.05.~~
~~PAGE 412~~
UG-01143 2015.05.11 Using PLLs and Clock Networks 3-49 For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL. Arria 10 transceivers support only fPLL to fPLL, fPLL to ATX PLL and ATX PLL to fPLL cascading. For PLL feedback compensation bonding, connections (2) and (4) are used to connect the master CGB's parallel clock output to the PLL feedback clock input port. PLL feedback compensation bonding can be used instead of xN bonding.
~~PAGE 413~~
3-50 UG-01143 2015.05.11 Implementing Multi-Channel x1 Non-Bonded Configuration Figure 3-19: PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded Configuration Example Transceiver PLL Instance (5 GHz) Native PHY Instance (1 CH Non-Bonded 10 Gbps) PLL TX Channel To implement this configuration, instantiate a PLL IP core and a PHY IP core and connect them together as shown in the above figure. Steps to implement a Single Channel x1 Non-Bonded Configuration 1.
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UG-01143 2015.05.11 Implementing Multi-Channel x1 Non-Bonded Configuration 3-51 Figure 3-20: PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded Configuration Transceiver PLL Instance (5 GHz) ATX PLL Native PHY Instance (10 CH Non-Bonded 10 Gbps) TX Channel TX Channel TX Channel TX Channel Transceiver PLL Instance (5 GHz) TX Channel ATX PLL TX Channel TX Channel TX Channel TX Channel TX Channel Legend: TX channels placed in the same transceiver bank.
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3-52 UG-01143 2015.05.11 Implementing Multi-Channel xN Non-Bonded Configuration Implementing Multi-Channel xN Non-Bonded Configuration Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock sources used. Figure 3-21: PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded Configuration In this example, the same PLL is used to drive 10 channels across two transceiver banks.
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UG-01143 2015.05.11 Bonded Configurations 3-53 • In this case, the PLL IP core has mcgb_serial_clk output port. This represents the xN clock line. • The Native PHY IP core has 10 (for this example) tx_serial_clk input ports. Each port corresponds to the input of the local CGB of the transceiver channel. • As shown in the figure above, connect the mcgb_serial_clk output port of the PLL IP core to the 10 tx_serial_clk input ports of the Native PHY IP core.
~~PAGE 417~~
3-54 UG-01143 2015.05.11 Implementing x6/xN Bonding Mode Implementing x6/xN Bonding Mode Figure 3-23: PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode Transceiver PLL Instance (5 GHz) ATX PLL x1 Native PHY Instance (10 CH x6/xN Bonding 10 Gbps) Master CGB x6 x6 TX Channel x6 TX Channel x6 TX Channel x6 TX Channel x6 TX Channel x6 TX Channel xN TX Channel xN TX Channel xN TX Channel xN TX Channel Legend: TX channels placed in the same transceiver bank.
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UG-01143 2015.05.11 Implementing PLL Feedback Compensation Bonding Mode 3-55 • In this case, the PLL IP core has tx_bonding_clocks output bus with width [5:0]. • The Native PHY IP core has tx_bonding_clocks input bus with width [5:0] multiplied by the number of transceiver channels (10 in this case). For 10 channels, the bus width will be [59:0]. Note: While connecting tx_bonding_clocks, leave pll_ref_clk open to avoid any Quartus II software fitter errors.
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~~3-56 UG-01143 2015.05.~~
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UG-01143 2015.05.11 Implementing PLL Cascading 3-57 • If you use the ATX PLL, set the following configuration settings: • Under the Master Clock Generation Block Tab • Enable Include Master Clock Generation Block. • Turn ON Enable Bonding Clock output ports. • Turn ON Enable feedback compensation bonding. • If you use the fPLL, set the following configuration settings: • Under the PLL Tab • Set the PLL Feedback type to feedback compensation bonding.
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3-58 UG-01143 2015.05.11 Implementing PLL Cascading Figure 3-26: PLL Cascading fPLL or ATX PLL (Cascade Source) pll_refclk0 pll_powerdown hssi_pll_cascade_clk pll_locked fPLL or ATX PLL (Transceiver PLL) pll_refclk0 pll_powerdown Steps to implement fPLL to ATX PLL cascading: 1. Instantiate the fPLL IP. Refer to Instantiating the fPLL IP Core on page 3-15 for detailed steps. 2.
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UG-01143 2015.05.11 Mix and Match Example 3-59 Mix and Match Example In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data rates. The following design example illustrates PLL sharing and both bonded and non-bonded clocking configurations. Figure 3-27: Mix and Match Design Example Transceiver Bank ATX PLL 6.25 GHz x6 MCGB Transceiver Bank xN ATX PLL 5.
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3-60 UG-01143 2015.05.11 Mix and Match Example Use the following data rates and configuration settings for PLL IP cores: • Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz • • • • • Enable the Master CGB and bonding output clocks. Transceiver PLL instance 1: ATX PLL with output clock frequency of 5.1625 GHz Transceiver PLL instance 2: ATX PLL with output clock frequency of 5.1625 GHz Transceiver PLL instance 3: ATX PLL with output clock frequency of 4.
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UG-01143 2015.05.11 Mix and Match Example 3-61 Native PHY IP Instances In this example, four Transceiver Native PHY IP instances and four 10GBASE-KR PHY IP instances are used. Use the following data rates and configuration settings for the PHY IPs: • 12.5 Gbps Interlaken with a bonded group of 10 channels • Set the Interlaken 10x12.5 Gbps preset from the Arria 10 Transceiver Native PHY IP GUI. • Refer to Interlaken on page 2-76 for more details. • Custom multi-data rate 1.25G/9.8G/10.
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3-62 UG-01143 2015.05.11 Timing Closure Recommendations Connection Guidelines for PLL and Clock Networks • For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the tx_bonding_clocks to the transceiver PLL's tx_bonding_clocks output port. Make this connection for all 10 bonded channels. This connection uses a master CGB and the x6 / xN clock line to reach all the channels in the bonded group.
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Resetting Transceiver Channels 4 2015.05.11 UG-01143 Subscribe Send Feedback To ensure that transceiver channels are ready to transmit and receive data, you must properly reset the transceiver PHY. Altera recommends a reset sequence that ensures the physical coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver channel initialize and function correctly. You can either use the Altera Reset Controller IP or create your own reset controller.
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4-2 UG-01143 2015.05.11 When Is Reset Required? When Is Reset Required? You can reset the transmitter (TX) and receiver (RX) data paths independently or together. The recommended reset sequence requires reset and initialization of the PLL driving the TX or RX channels, as well as the TX and RX datapaths.
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UG-01143 2015.05.11 Recommended Reset Sequence 4-3 Recommended Reset Sequence Figure 4-2: Transmitter and Receiver Reset Sequence 1 Transmit or Receive 2 FPGA Device Power Up/Operation 3 Ensure Calibration Completed 4 PLL,TX/RX Analog Reset Deasserted 5 Associated PLL/CDR Locked 6 Release TX/RX Digital Reset 7 TX/RX Reset Completed Resetting the Transmitter After Device Power-Up The FPGA automatically calibrates the PLL at every power-up before entering user-mode.
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4-4 UG-01143 2015.05.11 Resetting the Transmitter During Device Operation Figure 4-3: Transmitter Reset Sequence After Power-Up Device Power Up Device in User Mode pll_cal_busy tx_cal_busy pll_powerdown 1 tx_analogreset 1 pll_locked tx_digitalreset tpll_lock max 10 μs 2 ttx_digitalresetmin 20 ns 3 Resetting the Transmitter During Device Operation Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation.
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UG-01143 2015.05.11 Resetting the Receiver After Device Power-Up 4-5 Figure 4-4: Transmitter Reset Sequence During Device Operation Device Power Up pll_cal_busy tx_cal_busy pll_powerdown 1 tx_analogreset 1 tx_digitalreset 1 pll_locked tpll_powerdown min 1 µs 3 2 ttx_digitalreset min 20 ns tpll_lock max 10 µs Resetting the Receiver After Device Power-Up Follow this reset sequence to ensure a reliable receiver initialization after initial power-up.
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4-6 UG-01143 2015.05.11 Resetting the Receiver During Device Operation Figure 4-5: Receiver Reset Sequence Following Power-Up Device Power Up Device in User Mode 2 1 rx_analogreset trx_analogreset min 40 ns 3 rx_is_lockedtodata rx_digitalreset tLTD min 4 μs 4 rx_cal_busy Note: rx_is_lockedtodata might toggle when there is no data at the receiver input. rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted. rx_analogreset must always be followed by rx_digitalreset.
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UG-01143 2015.05.11 Clock Data Recovery in Manual Lock Mode 4-7 Clock Data Recovery in Manual Lock Mode Use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock mode depending on your design requirements. The two control signals to enable and control the CDR in manual lock mode are rx_set_locktoref and rx_set_locktodata. Related Information "Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP Core User Guide.
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~~4-8 UG-01143 2015.05.~~
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UG-01143 2015.05.11 Using the Altera Transceiver PHY Reset Controller Transceiver Block pll_powerdown tx_analogreset tx_digitalreset Transmitter Standard PCS Yes Transmitter Enhanced PCS Yes Transmitter PMA Transmitter PCIe Gen3 PCS rx_analogreset 4-9 rx_digitalreset Yes Yes Using the Altera Transceiver PHY Reset Controller Altera's Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in response to PLL lock activity.
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~~4-10 UG-01143 2015.05.~~
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UG-01143 2015.05.11 Parameterizing the Transceiver PHY Reset Controller IP 4-11 Parameterizing the Transceiver PHY Reset Controller IP This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Catalog. You can customize the following Transceiver PHY Reset Controller parameters for different modes of operation by clicking Tools > IP Catalog. To parameterize and instantiate the Transceiver PHY Reset Controller IP core: 1.
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4-12 UG-01143 2015.05.11 Transceiver PHY Reset Controller Parameters Name Range Enable TX PLL reset control On /Off pll_powerdown duration 1-999999999 Synchronize reset input for PLL powerdown Description When On, the Transceiver PHY Reset Controller IP core enables the reset control of the TX PLL. When Off, the TX PLL reset control is disabled. On /Off Specifies the duration of the PLL powerdown period in ns. The value is rounded up to the nearest clock cycle. The default value is 1000 ns.
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UG-01143 2015.05.11 Transceiver PHY Reset Controller Interfaces Name Range 4-13 Description RX Channel Enable RX channel reset control On /Off When On, the Transceiver PHY Reset Controller enables the control logic and associated status signals for RX reset. When Off, disables RX reset control and status signals. Use separate RX reset per channel On /Off When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels.
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4-14 UG-01143 2015.05.11 Transceiver PHY Reset Controller Interfaces Figure 4-9: Transceiver PHY Reset Controller IP Core Top-Level Signals Generating the IP core creates signals and ports based on your parameter settings.
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UG-01143 2015.05.11 Transceiver PHY Reset Controller Interfaces Signal Name Direction Clock Domain 4-15 Description Input Asynchronous This is calibration status signal from the Transceiver PHY IP core. When asserted, the initial calibration is active. When deasserted, calibration has completed. It will not be asserted if you manually re-trigger the calibra‐ tion IP. This signal gates the RX reset sequence. The width of this signals depends on the number of RX channels.
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4-16 UG-01143 2015.05.11 Transceiver PHY Reset Controller Interfaces Signal Name tx_digitalreset[-1:0] Direction Output Clock Domain Synchronous to the Transceiver PHY Reset Controller input clock. Description Digital reset for TX channels. The width of this signal depends on the number of TX channels.
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UG-01143 2015.05.11 Transceiver PHY Reset Controller Resource Utilization Signal Name rx_digitalreset[ -1:0] Direction Output Clock Domain Synchronous to the Transceiver PHY Reset Controller input clock. 4-17 Description Digital reset for RX. The width of this signal depends on the number of channels.
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4-18 UG-01143 2015.05.11 Using a User-Coded Reset Controller Configuration Combination ALUTs Four transceiver channels, shared TX reset, separate RX resets Logic Registers approximately 100 approximately 150 Using a User-Coded Reset Controller You can design your own user-coded reset controller instead of using Altera's Transceiver PHY Reset Controller IP core.
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UG-01143 2015.05.11 Combining Status or PLL Lock Signals 4-19 Table 4-7: User-coded Reset Controller, Transceiver PHY, and TX PLL Signals Signal Name Direction Description pll_powerdown Output Resets the TX PLL when asserted high. tx_analogreset Output Resets the TX PMA when asserted high. tx_digitalreset Output Resets the TX PCS when asserted high. rx_analogreset Output Resets the RX PMA when asserted high. rx_digitalreset Output Resets the RX PCS when asserted high.
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4-20 UG-01143 2015.05.11 Timing Constraints for Bonded PCS and PMA Channels Figure 4-11: Combining Multiple PHY Status Signals tx_cal_busy signals from channels AND OR To reset controller tx_cal_busy input port Note: This configuration also applies to the rx_cal_busy signals. When using multiple PLLs, you can logical AND the pll_locked signals feeding the reset controller. Similarly, you can logical OR the pll_cal_busy signals to the reset controller tx_cal_busy port as shown below.
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UG-01143 2015.05.11 Timing Constraints for Bonded PCS and PMA Channels 4-21 Figure 4-13: Physical Routing Delay Skew in Bonded Channels FPGA Fabric PHY Reset Controller tx_digitalreset TX Channel[ n - 1] TX Channel[1] Bonded TX Channels TX Channel[0] You must provide a Synopsys Design Constraint (SDC) for the reset signals to guarantee that your design meets timing requirements. The Quartus II software generates an .sdc file when you generate the Transceiver Native PHY IP. This .
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~~4-22 Timing Constraints for Bonded PCS and PMA Channels UG-01143 2015.05.11 For more information about the set_max_skew constraint, refer to the SDC and TimeQuest API Reference Manual.~~
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5 Arria 10 Transceiver PHY Architecture 2015.05.11 UG-01143 Subscribe Send Feedback Arria 10 PMA Architecture The Physical Medium Attachment (PMA) acts as the analog front end for the Arria 10 transceivers. The PMA receives and transmits high-speed serial data depending on the transceiver channel configura‐ tion. All serial data transmitted and received passes through the PMA. Transmitter The transmitter takes the parallel data and serializes it to create a high-speed serial data stream.
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~~5-2 UG-01143 2015.05.11 Transmitter Buffer Figure 5-2: Serializer Block The serializer block sends out the least significant bit (LSB) of the input data first.~~
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UG-01143 2015.05.11 High Speed Differential I/O 5-3 Figure 5-3: Transmitter Buffer To Serial Data Output Pins (tx_serial_data) Programmable Pre-Emphasis and VOD Receiver Detect On-Chip Termination 85Ω, 100Ω, OFF TX V CM High Speed Differential I/O To improve performance, Arria 10 Transmitter uses a new architecture in the output buffer—High Speed Differential I/O.
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5-4 UG-01143 2015.05.11 Programmable Pre-Emphasis Programmable Pre-Emphasis Pre-emphasis can maximize the eye at the far-end receiver. The programmable pre-emphasis module in each transmit buffer amplifies high frequencies in the transmit data signal, to compensate for attenuation in the transmission media. The pre-tap pre-emphasizes the bit before the transition and de-emphasizes the remaining bits. A different polarity on pre-tap does the opposite.
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UG-01143 2015.05.11 Receiver Buffer 5-5 Figure 5-5: Receiver PMA Block Diagram Receiver PMA Receiver Serial Differential Input Data Receiver Buffer Serial Data CDR Serial Data Deserializer Parallel Data Receiver PCS Parallel Data FPGA Fabric Serial Clock Parallel Clock Receiver Buffer The receiver input buffer receives serial data from rx_serial_data and feeds the serial data to the clock data recovery (CDR) unit and deserializer.
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5-6 UG-01143 2015.05.11 Programmable Differential On-Chip Termination (OCT) Note: On-chip biasing circuitry is available only if you select OCT. If you select external termination, you must implement off-chip biasing circuitry to establish the VCM at the receiver input buffer. Programmable Differential On-Chip Termination (OCT) Receiver buffers include programmable on-chip differential termination of 85Ω, 100Ω, or OFF. You can disable OCT and use external termination.
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UG-01143 2015.05.11 High Data Rate Mode 5-7 Figure 5-7: CTLE DC and AC Gain Conceptualization Gain (dB) DC Gain Control Frequency AC Gain Control Gain (dB) Frequency Note: Final equalization curves will be available in the Arria 10 device datasheet. High Data Rate Mode High Data Rate Mode is a low power mode that supports data rate up to 28.3 Gbps. This mode provides an alternative path for high gain mode. High Data Rate Mode can be used to compensate for the loss similar to CEI 28G VSR.
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5-8 UG-01143 2015.05.11 Variable Gain Amplifier (VGA) When CTLE adaptation is disabled (manual mode), you can select CTLE mode and set CTLE gain through the Quartus Assignment Editor /.qsf and the Avalon-MM registers. Supported modes for CTLE: • Manual Mode: 1. In this mode, manual CTLE values can be set in Assignment Editor/.qsf or using Avalon MM interface. • Triggered Adaptation Mode 1. In this adaptation mode, CTLE gain values are controlled by the Adaptive Parametric Tuning Engine.
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UG-01143 2015.05.11 Decision Feedback Equalization (DFE) 5-9 Supported modes for VGA: • Manual Mode: • In this mode, manual VGA values can be set in Assignment Editor/.qsf or using Avalon MM interface. • Triggered Adaptation Mode: • In this adaptation mode, VGA gain values are controlled by the Adaptive Parametric Tuning Engine. This mode uses the converged VGA values given by the Adaptive Parametric Tuning Engine. VGA adaptation mode is synched-up with CTLE adaptation mode.
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5-10 UG-01143 2015.05.11 Decision Feedback Equalization (DFE) Figure 5-9: Signal ISI ISI+ ISI- Precursor Cursor Postcursor Notes: • An ideal pulse response is a single data point at the cursor. • Real world pulse response is non-zero before the cursor (precursor) and after the cursor (postcursor). • ISI occurs when the data sampled at precursor or postcursor is not zero. The DFE circuit stores delayed versions of the data.
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UG-01143 2015.05.11 Decision Feedback Equalization (DFE) 5-11 Figure 5-10: Channel Pulse Response V Signal at the Channel Input Region of Influence for Fixed Taps Signal at the Channel Output 1U I t Note: The pulse at the output of the channel shows a long decaying tail. Frequency-dependent losses and quality degradation affects other signals. Supported modes for DFE: • Disabled Mode: • DFE disabled mode is similar to DFE manual mode, except all DFE tap values in this mode are set to zero.
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5-12 UG-01143 2015.05.11 How to Enable CTLE and DFE How to Enable CTLE and DFE Table 5-2: Summary of Receiver Equalization Modes Receiver Equalization Modes CTLE adaptation mode Triggered, Manual DFE adaptation mode Continuous, Manual, Disabled Number of fixed DFE taps 3,7 Note: For a high speed link that requires both CTLE and DFE, you can use all combinations of CTLE and DFE modes shown in the table above. For example: Use CTLE in manual or triggered mode with DFE in continuous mode.
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UG-01143 2015.05.11 On-Die Instrumentation (ODI) 5-13 a. For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using the reconfigura‐ tion interface. The values are written dynamically and do not require design re-compilation. Refer to Arria 10 Register Map for details on the specific registers that set the CTLE gain values/DFE taps. b. For dynamically changing CTLE or DFE Adaptation mode, refer to the Arria 10 Register Map and Arria 10 Adaptation Tool for the list of adaptation registers.
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5-14 UG-01143 2015.05.11 Clock Data Recovery (CDR) Unit Figure 5-12: CDR Sample and ODI Sample to Calculate Bit Error Ratio 64 Steps ODI Sample CDR Sample 128 Steps Vertical Offset Horizontal Offset Clock Data Recovery (CDR) Unit The PMA of each channel includes a channel PLL that you can configure as a receiver clock data recovery (CDR) for the receiver. You can also configure the channel PLL of channels 1 and 4 as a clock multiplier unit (CMU) PLL for the transmitter in the same bank.
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UG-01143 2015.05.11 Lock-to-Data Mode 5-15 signal is asserted active high to indicate that the CDR has locked to the phase and frequency of the receiver input reference clock. Note: The phase detector (PD) is inactive in LTR mode. Lock-to-Data Mode During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input.
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5-16 UG-01143 2015.05.11 Deserializer CDR Lock Mode rx_set_locktoref rx_set_locktodata 1 0 Manual-RX CDR LTR X 1 Manual-RX CDR LTD Deserializer The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA fabric.
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UG-01143 2015.05.11 5-17 Loopback Figure 5-15: Serial Loopback Path The serial loopback path sets the CDR to recover the data from serializer while data from receiver serial input pin is ignored by CDR. The transmitter buffer sends data normally.
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5-18 UG-01143 2015.05.11 Arria 10 Enhanced PCS Architecture Figure 5-17: Reverse Loopback Path/Post CDR The reverse loopback path sets the transmitter buffer to transmit data fed directly from the CDR recovered data. Data from the serializer is ignored by the transmitter buffer.
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~~UG-01143 2015.05.~~
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5-20 UG-01143 2015.05.11 Phase Compensation Mode The TX FIFO supports the following operating modes: • • • • Phase Compensation mode Register mode Interlaken mode Basic mode Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 6-1 Phase Compensation Mode In Phase Compensation mode, the TX FIFO decouples phase variations between the FPGA fabric and transceiver clock domains. In this mode, the TX FIFO compensates for the phase difference between the read and write clocks.
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UG-01143 2015.05.11 Interlaken Mode 5-21 Interlaken Mode In Interlaken mode, the TX FIFO operates as an elastic buffer. In this mode, there are additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You control the writing to the TX FIFO with tx_enh_data_valid by monitoring the FIFO flags. The goal is to prevent the FIFO from becoming full or empty.
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5-22 UG-01143 2015.05.11 64B/66B Encoder and Transmitter State Machine The CRC-32 calculation covers most of the metaframe, including the diagnostic word, except the following: • Bits [66:64] of each word • 58-bit scrambler state within the scrambler state word • 32-bit CRC-32 field within the diagnostic word Figure 5-20: Interlaken CRC-32 Generator The Interlaken CRC-32 generator implements the Interlaken protocol.
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~~UG-01143 2015.05.~~
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5-24 UG-01143 2015.05.11 PRBS Pattern Generator (Shared between Enhanced and Standard PCSes) PCS-PMA width only. The PRBS generator patterns can only be used when PCS-PMA interface width is configured to 10 bits or 64 bits.
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UG-01143 2015.05.11 Pseudo-Random Pattern Generator 5-25 Figure 5-23: Generator for Square Wave Pattern n 0s n 1s n is a programmable number of consecutive serial bit 1s and 0s. n is 1, 4, or 8 (n defaults to 4). Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
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5-26 UG-01143 2015.05.11 Interlaken Disparity Generator Figure 5-24: Asynchronous Scrambler in Serial Implementation IN S0 S1 S2 S38 S39 S56 S57 OUT In synchronous mode, the scrambler is initially reset to different programmable seeds on each lane. The scrambler then runs by itself. Its current state is XOR’d with the data to generate scrambled data. A data checker in the scrambler monitors the data to determine if it should be scrambled or not.
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UG-01143 2015.05.11 TX Gearbox, TX Bitslip and Polarity Inversion 5-27 Table 5-5: Inversion Bit Definition Bit 66 Interpretation 0 Bits [63:0] are not inverted; the receiver processes this word without modification 1 Bits [63:0] are inverted; the receiver inverts the bits before processing this word Note: The Interlaken disparity generator is available to implement the Interlaken protocol.
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5-28 UG-01143 2015.05.11 KR FEC Blocks KR FEC Blocks The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10G-KRFEC and 40GKRFEC of the IEEE 802.3 specification. The KR FEC implements the Forward Error Correction (FEC) sublayer, a sublayer between the PCS and PMA sublayers. Most data transmission systems, such as Ethernet, have minimum requirements for the bit error rate (BER). However, due to channel distortion or noise in the channel, the required BER may not be achievable.
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UG-01143 2015.05.11 Receiver Datapath 5-29 KR FEC TX Gearbox The KR FEC TX gearbox converts 65-bit input words to 64-bit output words to interface the KR FEC encoder with the PMA. This gearbox is different from the TX gearbox used in the Enhanced PCS. The KR FEC TX gearbox aligns with the FEC block. Because the encoder output (also the scrambler output) has its unique word size pattern, the gearbox is specially designed to handle that pattern.
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5-30 UG-01143 2015.05.11 Descrambler Descrambler The descrambler block descrambles received data to regenerate unscrambled data using the x58 + x39 +1 polynomial. Like the scrambler, it operates in asynchronous mode or synchronous mode. Related Information Scrambler on page 5-25 Interlaken Frame Synchronizer The Interlaken frame synchronizer delineates the metaframe boundaries and searches for each of the framing layer control words: Synchronization, Scrambler State, Skip, and Diagnostic.
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UG-01143 2015.05.11 Pseudo Random Pattern Verifier PRBS Pattern 10 bit PCS-PMA width 5-31 64 bit PCS-PMA width PRBS15: x15 + x14 + 1 Yes PRBS23: x23 + x18 + 1 Yes PRBS31: x31 + x28 + 1 Yes Figure 5-30: PRBS9 Verify Serial Implementation PRBS datain S0 S1 S4 S5 S8 PRBS Error The PRBS checker has the following control and status signals available to the FPGA fabric: • rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr.
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5-32 UG-01143 2015.05.11 10GBASE-R Bit-Error Rate (BER) Checker Figure 5-31: PRP Verifier Error Counter error_count Descrambler Test Pattern Detect Pseudo Random Verifier Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
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UG-01143 2015.05.11 Phase Compensation Mode 5-33 The RX FIFO supports the following modes: • • • • • Phase Compensation mode Register mode Interlaken mode (deskew FIFO) 10GBASE-R mode (clock compensation FIFO) Basic mode (elastic buffer FIFO) Phase Compensation Mode The RX FIFO compensates for the phase difference between the read clock and write clocks. rx_clkout (RX parallel low-speed clock) clocks the write side of the RX FIFO.
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5-34 UG-01143 2015.05.11 10GBASE-R Mode Figure 5-32: RX FIFO as Interlaken Deskew FIFO FPGA Fabric Interface rx_enh_fifo_align_clr rx_enh_fifo_rd_en User Deskew FSM rx_enh_fifo_pempty RX FIFO rx_enh_fifo_pfull 10GBASE-R Mode In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the block synchronizer achieves block lock, data is sent through the FIFO.
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UG-01143 2015.05.11 Idle Insertion 5-35 Figure 5-33: IDLE Word Deletion This figure shows the deletion of IDLE words from the receiver data stream. Before Deletion rx_parallel_data 00000000000004ADh 00000000000004AEh 0707070707FD0000h 000000FB07070707h 00000000000004AEh 0707070707FD0000h AAAAAAAA000000FBh After Deletion rx_parallel_data 00000000000004ADh Idle Deleted Figure 5-34: OS Word Deletion This figure shows the deletion of Ordered set words in the receiver data stream.
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5-36 UG-01143 2015.05.11 Basic Mode Figure 5-35: IDLE Word Insertion This figure shows the insertion of IDLE words in the receiver data stream. rx_parallel_data Before Insertion FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh After Insertion rx_parallel_data FD000000000004AEh Idle Inserted Basic Mode In Basic mode, the RX FIFO operates as an elastic buffer.
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UG-01143 2015.05.11 Arria 10 Standard PCS Architecture 5-37 Arria 10 Standard PCS Architecture The standard PCS can operate at a data rate up to 12 Gbps. Protocols such as PCI-Express, CPRI 4.2+, GigE, IEEE 1588 are supported in Hard PCS while the other protocols can be implemented using Basic/ Custom (Standard PCS) transceiver configuration rules.
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5-38 UG-01143 2015.05.11 TX FIFO Low Latency Mode Figure 5-37: TX FIFO Block Diagram Datapath to Byte Serializer, 8B/10B Encoder, or Serializer TX FIFO rd_clk tx_clkout Datapath from FPGA Fabric or PIPE Interface wr_clk tx_coreclkin The TX FIFO read port is clocked by the low speed parallel clock and its write port is clocked by either tx_clkout or tx_coreclkin. The tx_clkout signal is used when only one channel is being used. The tx_coreclkin signal is used when using multiple channels.
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5-40 UG-01143 2015.05.11 8B/10B Encoder In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the parallel data width from the TX FIFO is divided four times, the clock rate is quadrupled. After byte serialization, the byte serializer forwards the least significant word first followed by the most significant word.
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UG-01143 2015.05.11 8B/10B Encoder Control Code Encoding 5-41 8B/10B Encoder Control Code Encoding Figure 5-40: Control Code Encoding Diagram tx_clkout tx_parallel_data[15:0] tx_datak[1:0] Code Group D3.4 8378 BCBC 0 1 D24.3 D28.5 0F00 BF3C 0 K28.5 D15.0 D0.0 D31.5 D28.1 The tx_datak signal is used to indicate whether the 8-bit data being sent at the tx_parallel_data port should be a control word or a data word. When tx_datak is high, the 8-bit data is encoded as a control word (Kx.y).
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5-42 UG-01143 2015.05.11 8B/10B Encoder Bit Reversal Feature 8B/10B Encoder Bit Reversal Feature The bit reversal feature reverses the order of the bits of the input data. Bit reversal is performed at the output of the 8B/10B Encoder and is available even when the 8B/10B Encoder is disabled. For example, if the input data is 20-bits wide, bit reversal switches bit [0] with bit [19], bit [1] with bit [18] and so on.
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5-44 UG-01143 2015.05.11 Word Aligner Synchronous State Machine Mode a new word boundary. If rx_std_wa_patternalign is deasserted, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary. The rx_syncstatus and rx_patterndetect signals, with the same latency as the datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
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5-46 UG-01143 2015.05.11 Word Aligner Pattern Length for Various Word Aligner Modes PCS-PMA Interface Width Supported Word Aligner Modes Supported Word Aligner Pattern Lengths rx_std_wa_ patternalign rx_syncstatus rx_patterndetect behavior behavior behavior BITSLIP signal toggles.
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UG-01143 2015.05.11 Word Aligner Pattern Length for Various Word Aligner Modes PCS-PMA Interface Width Supported Word Aligner Modes Supported Word Aligner Pattern Lengths rx_std_wa_ patternalign behavior 5-47 rx_syncstatus rx_patterndetect behavior behavior when the FPGA fabric-asserted BITSLIP signal toggles. Manual 8, 16, 32 Word alignment Stays high after is controlled by the word aligner rising-edge of aligns to the rx_std_wa_ word alignment patternalign. pattern.
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5-48 UG-01143 2015.05.11 Word Aligner RX Bit Reversal Feature PCS-PMA Interface Width Supported Word Aligner Modes Manual Supported Word Aligner Pattern Lengths rx_std_wa_ patternalign rx_syncstatus rx_patterndetect behavior behavior behavior 7, 10, 20, 40 Word alignment Stays high after is controlled by the word aligner rising edge of aligns to the rx_std_wa_ word alignment patternalign. pattern.
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UG-01143 2015.05.11 Word Aligner RX Byte Reversal Feature 5-49 from the PMA is a 10-bit data width, the bit reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled, changes the data to 1100100001. Word Aligner RX Byte Reversal Feature The RX byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits.
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5-50 UG-01143 2015.05.11 8B/10B Decoder • Rate Match FIFO Basic (Double Width) Mode on page 2-300 For more information about implementing rate match FIFO in basic double width mode. • How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers on page 2-104 For more information about implementing rate match FIFO in GigE mode. • PCI Express (PIPE) on page 2-228 For more information about implementing rate match FIFO in PCIe mode.
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UG-01143 2015.05.11 5-51 8B/10B Decoder Control Code Encoding 8B/10B Decoder Control Code Encoding Figure 5-43: 8B/10B Decoder in Control Code Group Detection When the PCS-PMA Interface Width is 10 Bits tx_clkout TX datain[9:0] D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D3.4 83 78 BC BC 0F 00 BF 83 rx_datak RX dataout[7:0] When the PCS-PMA Interface Width is 20 Bits tx_clkout TX datain[19:10] D3.4 D28.5 D15.0 D3.4 D3.4 D28.5 D15.0 D3.4 D24.3 K28.5 D15.0 D3.4 D24.3 K28.
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5-52 UG-01143 2015.05.11 Byte Deserializer Byte Deserializer The byte deserializer allows the transceiver to operate at data rates higher than those supported by the FPGA fabric. It deserializes the recovered data by multiplying the data width two or four times, depending upon the deserialization mode selected. The byte deserializer is optional in designs that do not exceed the FPGA fabric interface frequency upper limit.
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UG-01143 2015.05.11 Bonded Byte Deserializer 5-53 Bonded Byte Deserializer The bonded byte deserializer is also available for channel-bundled applications such as PIPE. In this configuration, the control signals of the byte deserializers of all the channels are bonded together. A master channel controls all the other channels to prevent skew between the channels.
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5-54 UG-01143 2015.05.11 Transmitter Datapath This section will focus on the basic blocks of PIPE 3.0-based Gen3 PCS architecture. The PIPE 3.0-based Gen3 PCS uses a 128b/130b block encoding/decoding scheme, which is different from the 8B/10B scheme used in Gen1 and Gen2. The 130-bit block contains a 2-bit sync header and a 128-bit data payload. For this reason, Arria 10 devices include a separate Gen3 PCS that supports functionality at Gen3 speeds.
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UG-01143 2015.05.11 TX FIFO (Shared with Standard and Enhanced PCS) 5-55 TX FIFO (Shared with Standard and Enhanced PCS) The TX FIFO in each channel ensures a reliable transfer of data and status signals between the PCS channel and the FPGA fabric. The TX FIFO compensates for the phase difference between the low speed parallel PCS clock and the FPGA fabric clock. The RX and TX FIFOs are shared with standard and enhanced PCS. In Hard IP mode, the TX FIFO works in register mode.
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5-56 UG-01143 2015.05.11 Rate Match FIFO Rate Match FIFO In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. Frequency differences in the order of a few hundred PPM can corrupt the data when latching from the recovered clock domain to the local receiver reference clock domain.
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UG-01143 2015.05.11 Clock Data Recovery Control 5-57 Related Information Rate Switch on page 2-235 Clock Data Recovery Control The CDR control feature is used for the L0s fast exit when operating in PIPE Gen3 mode. Upon detecting an Electrical Idle Ordered Set (EIOS), this feature takes manual control of the CDR by forcing it into a lock-to-reference mode. When an exit from electrical idle is detected, this feature moves the CDR into lock-to-data mode to achieve fast data lock.
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Reconfiguration Interface and Dynamic Reconfiguration 6 2015.05.11 UG-01143 Subscribe Send Feedback This chapter explains the purpose and the use of the Arria 10 reconfiguration interface that is part of the Transceiver Native PHY IP core and the Transceiver PLL IP core. Dynamic reconfiguration is the process of dynamically modifying transceiver channels and PLLs to meet changing requirements during device operation.
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6-2 UG-01143 2015.05.11 Reconfiguration Interface and Dynamic Reconfiguration master is connected to the Avalon-MM reconfiguration interface. Communication with the channel and PLL reconfiguration interface requires an Avalon-compliant master.
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6-4 UG-01143 2015.05.11 Interacting with the Reconfiguration Interface Interacting with the Reconfiguration Interface Each transmit PLL and channel has a dedicated Avalon-MM slave interface. The transmit PLL instance has a maximum of one reconfiguration interface. Unlike the PLL instance, the Native PHY instance can specify multiple channels.
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UG-01143 2015.05.11 Writing to the Reconfiguration Interface 6-5 Figure 6-3: Reading from the Reconfiguration Interface reconfig_clk reconfig_reset reconfig_address 119 reconfig_read reconfig_readdata XXXX VALID XXXX reconfig_waitrequest reconfig_write reconfig_writedata XXXX Writing to the Reconfiguration Interface Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL IP core changes the data value at a specific address.
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6-6 UG-01143 2015.05.11 Configuration Files Figure 6-4: Writing to the Reconfiguration Interface reconfig_clk reconfig_reset reconfig_waitrequest reconfig_address 119 reconfig_read reconfig_readdata 00000000 reconfig_write reconfig_writedata 0000000c Related Information Ports and Parameters on page 6-24 Configuration Files You can save the parameters you specify for the Transceiver Native PHY and Transmit PLL IP instances as configuration files.
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UG-01143 2015.05.11 Configuration Files 6-7 32'h00000000; localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE = 1'h0; The SystemVerilog configuration files contain two parts. The first part consists of a data array of 26-bit hexadecimal values. The second part consists of parameter values. For the data array, each 26-bit hexadec‐ imal value is associated with a comment that describes the various bit positions.
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6-8 UG-01143 2015.05.11 Configuration Files Table 6-3: Transceiver Native PHY or PLL IP Parameters (Base and Modified Configurations) Native PHY Instance Required Parameter Settings Saved In Base • Click Interfaces > Transceiver PHY > Arria 10 • /reconfig/altera_xcvr_ ration core. Or, select one of the supported transmit PLL IP native_a10_reconfig_parameters.sv cores under PLL.
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UG-01143 2015.05.11 Multiple Reconfiguration Profiles 6-9 Multiple Reconfiguration Profiles You can optionally enable multiple configurations or profiles in the same Native PHY IP Parameter Editor for performing dynamic reconfiguration of PCS parameters. This allows the IP Parameter Editor to create, store, and analyze the parameter settings for multiple configurations or profiles.
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6-12 UG-01143 2015.05.11 Steps to Perform Dynamic Reconfiguration Steps to Perform Dynamic Reconfiguration You can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfiguration interface. The following figure shows the steps required to reconfigure the channel and PLL blocks.
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UG-01143 2015.05.11 Direct Reconfiguration Flow 6-13 Related Information • Embedded Debug Features on page 6-40 • Calibration on page 7-1 Direct Reconfiguration Flow Use this flow to perform dynamic reconfiguration when you know exactly which parameter and value to change for the transceiver channel or PLL. Refer to the Arria 10 Register Map for the feature address and bit locations of the feature you want to change. Perform a read-modify-write to reconfigure the transceiver channel or PLL.
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6-14 UG-01143 2015.05.11 Changing PMA Analog Parameters PMA Analog Feature Address Pre-emphasis 1st pre-tap polarity 0x107 Bit [5] Values 1'b0 = positive 1'b1 = negative Pre-emphasis 2nd pre-tap 0x108 [2:0] 3'b000 - 3'b111 Pre-emphasis 2nd pre-tap polarity 0x108 [4] 1'b0 = positive 1'b1 = negative Differential output voltage (VOD) 0x109 [4:0] 5'b00000 - 5'b11111 The PMA analog settings are governed by a set of rules. Not all combinations of VOD and pre-emphasis are valid.
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UG-01143 2015.05.11 Changing CTLE Settings in Manual Mode 6-15 Changing CTLE Settings in Manual Mode To change the CTLE settings in manual mode, you can either update the Quartus II Settings File (.qsf) with a known assignment, or follow the instructions below to perform a read-modify-write to the configu‐ ration registers using the reconfiguration interface. 1. Read from the CTLE feature address of the channel you want to change.
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6-16 UG-01143 2015.05.11 Enabling and Disabling Loopback Modes Serial Loopback Mode In serial loopback mode, a path exists between the serializer of the transmitter and the CDR of the receiver, so that the data from the CDR is recovered from the serializer while the data from the receiver serial input pin is ignored. You can enable or disable this mode.
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UG-01143 2015.05.11 Enabling and Disabling Loopback Modes 6-17 Table 6-8: Bit Values to Be Set Address Bit Values 0x137[7] 1’b1 0x13C[7] 1’b0 0x132[5:4] 2’bxx 0x142[4] 1’b1 0x11D[0] 1’b1 Reverse Serial Loopback Mode (Post-CDR) In the post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. Perform read-modify-write to the following registers to enable this mode.
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6-18 UG-01143 2015.05.11 IP Guided Reconfiguration Flow Address Bit Values 0x13C[7] 1’b0 0x132[5:4] 2’b00 0x142[4] 1’b0 0x11D[0] 1’b0 IP Guided Reconfiguration Flow Use the IP guided reconfiguration flow to perform dynamic reconfiguration when you need to change multiple parameters or parameters in multiple addresses for the transceiver channel or PLL. You can use this flow to change data rates, change clock divider values, or switch from one PCS datapath to another.
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6-20 UG-01143 2015.05.11 Switching Reference Clocks Table 6-11: Register Map for Switching Transmitter PLLs Transceiver Native PHY Port tx_serial_clk0 tx_serial_clk1 tx_serial_clk2 tx_serial_clk3 N/A Description Address Bits Represents logical PLL0. Lookup register x117[3:0] stores the mapping from logical PLL0 to the physical PLL. 0x117 (Lookup Register) [3:0] Represents logical PLL1. Lookup register x117[7:4] stores the mapping from logical PLL1 to the physical PLL.
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UG-01143 2015.05.11 6-21 ATX Reference Clock Switching ATX Reference Clock Switching You can use the reconfiguration interface on the ATX PLL instance to specify which reference clock source drives the ATX PLL. The ATX PLL supports clocking up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the Parameter Editor.
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6-22 UG-01143 2015.05.11 fPLL Reference Clock Switching fPLL Reference Clock Switching You can use the reconfiguration interface on the fPLL instance to specify which reference clock source drives the fPLL. The fPLL supports clocking by up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the reconfiguration interface.
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UG-01143 2015.05.11 6-23 CDR and CMU Reference Clock Switching Transceiver fPLL Port pll_refclk2 pll_refclk3 pll_refclk4 N/A Description Address Bits Represents logical refclk2 for MUX_1. Lookup 0x11F (Lookup register x11F[4:0] stores the mapping from Register) logical refclk2 to the physical refclk for MUX_1. [4:0] Represents logical refclk3 for MUX_1. Lookup 0x120 (Lookup register x120[4:0] stores the mapping from Register) logical refclk3 to the physical refclk for MUX_1.
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6-24 UG-01143 2015.05.11 Ports and Parameters Table 6-15: Register Map for Switching CDR Reference Clock Inputs Native PHY Port cdr_refclk0 cdr_refclk1 cdr_refclk2 cdr_refclk3 cdr_refclk4 N/A Description Address Bits Represents logical refclk0. Lookup register x16A[7:0] stores the mapping from logical refclk0 to the physical refclk. 0x16A (Lookup Register) [7:0] Represents logical refclk1. Lookup register x16B[7:0] stores the mapping from logical refclk1 to the physical refclk.
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UG-01143 2015.05.11 Ports and Parameters 6-25 You can share the reconfiguration interface among all the channels by turning on Share reconfiguration interface when parameterizing the IP core. When this option is enabled, the IP core presents a single reconfiguration interface for dynamic reconfiguration of all channels. Address bits [9:0] provide the register address in the reconfiguration space of the selected channel.
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6-26 UG-01143 2015.05.11 Ports and Parameters Port Name Direction Output reconfig_waitrequest Clock Domain reconfig_clk Description A one-bit signal that indicates the Avalon interface is busy. Keep the Avalon command asserted until this signal goes low. When Share reconfiguration interface is off, the Native PHY IP provides an independent reconfigura‐ tion interface for each channel.
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UG-01143 2015.05.11 Ports and Parameters Port Name Direction Clock Domain reconfig_readdata[N*32-1:0] Output reconfig_clk reconfig_waitrequest[N-1:0] Output reconfig_clk 6-27 Description A 32-bit data read bus for each channel. Valid data is placed on this bus after a read operation. Signal is valid after waitrequest goes high and then low. A one-bit signal for each channel that indicates the Avalon interface is busy. Keep the Avalon command asserted until this signal goes low.
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6-28 UG-01143 2015.05.11 Ports and Parameters Parameter Value Description Enable ODI acceleration logic On / Off Enables soft logic for accelerating bit and error accumulation when using ODI. Configuration file prefix Userspecified Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY.
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UG-01143 2015.05.11 Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks Parameter Value 6-29 Description Clear all profiles N/A Clears the Native PHY parameter settings for all the profiles. Refresh selected_profile N/A Equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence.
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UG-01143 2015.05.11 On-Die Instrumentation 6-31 For Native PHY 1—receive-only instance to be merged with Native PHY 0: set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to topdesign:topdesign_inst|*twentynm_hssi_avmm_if_inst* Example 6-3: Using pin names This example shows how to merge a transmit-only Native PHY instance with a receive-only instance using pin names. These instances are assigned to reconfiguration group 1.
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6-32 UG-01143 2015.05.11 On-Die Instrumentation Figure 6-15: ODI Block Diagram Receiver Input CTLE DFE CDR Deserializer ODI Avalon-MM Interface To PCS/FPGA Fabric Deserializer Phase Interpolator Logic Vref Generator ODI Sampler Bit Error Ratio Checker To Avalon-MM Interface Deserializer Table 6-19: Register Map for ODI Circuitry Address 0x143 Bits [1:0] Read / Write RW Feature Enable ODI Description These two bits are used to enable the eye monitor.
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6-38 UG-01143 2015.05.11 Using ODI to Build On-chip Eye Process Address 0x14C Bits [5:0] Read / Write RW Feature Status Selection Description Select the status signals presented in Status Value (address 0x177). The following encodings are used by ODI: • • • • • 6'h29: ODI Pattern Counter bits[7:0] 6'h2A: ODI Pattern Counter bits[15:8] 6'h2B: ODI Pattern Error bits[7:0] 6'h2C: ODI Pattern Error bits[15:8] 6'h2D: ODI Status bits • Bit 0: Busy.
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UG-01143 2015.05.11 Start Pattern Checker 6-39 a. Set ODI with DFE Enable to 1’b0 to use ODI with DFE disabled. Use ODI with DFE enabled will be supported in future b. Set Vertical Height to 6’h00 to select middle point in vertical c. Set Horizontal Phase to 7’h71 to select horizontal phase 1 d. Set ODI Pattern Filter to 2’b00 to set pattern filter “0” e. Refer to Start Pattern Checker on page 6-39 to see how many pattern errors are received f. Set ODI Pattern Filter to 2’b01 to set pattern filter “1” g.
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6-40 UG-01143 2015.05.11 Embedded Debug Features e. Set Status Selection in address 0x144 to 6’h2C to select the ODI Pattern Error bits[15:8] in Status value. f. Read Status value in address 0x177 to get the Pattern Error bits[15:8]. g. Set Status Selection in address 0x144 to 6’h2B to select the ODI Pattern Error bits[7:0] in Status value. h. Read Status value in address 0x177 to get Pattern Error bits[7:0]. i. You can repeat step “2.e.ii” to check whether more patterns are required.
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UG-01143 2015.05.11 Control and Status Registers 6-41 Table 6-23: Capability Registers for the Native PHY IP Core Address Type Name Description 0x200[7:0] RO IP Identifier Unique identifier for the Native PHY IP instance. 0x204[0] RO Status Register Enabled Indicates whether the status registers have been enabled. 1'b1 indicates that the status registers are enabled. 0x205[0] RO Control Register Enabled Indicates whether the control registers have been enabled.
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~~6-42 UG-01143 2015.05.11 Control and Status Registers The following control and status registers are available for the Native PHY IP core.~~
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UG-01143 2015.05.11 Control and Status Registers Address Type 0x2E2[6] RW 0x2E2[7] RW Register override_tx_ analogreset override_tx_ digitalreset 6-43 Description Selects whether the receiver listens to the ADME tx_analogreset register or the tx_ analogreset port. 1'b1 indicates the receiver listens to the ADME tx_analogreset register. Selects whether the receiver listens to the ADME tx_digitalreset register or the tx_ digitalreset port.
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6-44 UG-01143 2015.05.11 PRBS Soft Accumulators PRBS Soft Accumulators The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in conjunction with the hard PRBS blocks in the transceiver channel. This section describes the soft logic that can be added to the Native PHY IP core. To enable this option, turn on the Enable PRBS Soft Accumulators option in the Native PHY IP Parameter Editor. The PRBS has three control bits (Enable, Reset, and Snapshot) and one status bit (PRBS Done).
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6-46 UG-01143 2015.05.11 ODI Acceleration Logic ODI acceleration logic is available whether ADME is instantiated separately or as part of the Native PHY IP. To enable ODI acceleration logic with the Native PHY IP: 1. Enable dynamic reconfiguration 2. Enable the shared reconfiguration interface 3. Enable ODI acceleration logic To control the acceleration logic, three registers are available: • Enable—starts and stops the acceleration logic. • Reset—resets the counters.
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6-48 UG-01143 2015.05.11 Using PRBS and Square Wave Data Pattern Generator and Checker Linear Feedback Shift Register (LFSR), the next pattern can be determined from the previous pattern. When the PRBS checker receives a portion of the received pattern, it can generate the next sequence of bits to verify the next data sequence received is correct. The PRBS generator and checker in Arria 10 devices are hardened blocks shared between the Standard and Enhanced datapaths through the PCS.
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UG-01143 2015.05.11 Enabling the PRBS and Square Wave Data Generator 6-49 Table 6-32: Square Wave Supported Polynomials and Data Widths Pattern Square Wave Polynomial 64-Bit Number of consecutive 1s and 0s: 1, 4, 8 10-Bit X Enabling the PRBS and Square Wave Data Generator You must perform a sequence of read-modify-writes to addresses 0x006, 0x007, 0x008, and 0x110 to enable either the PRBS or square wave data generator.
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6-50 UG-01143 2015.05.11 Enabling the PRBS and Square Wave Data Generator Reconfigu‐ Reconfigu‐ ration ration Bit Address (HEX) 0x007 [7:4] [3:0] Attribute Name prbs_gen_pat Related Addresses 0x8 Attribute Encoding Bit Encoding Description prbs_7 4'b0001 Enable PRBS7 pattern prbs_9 4'b0010 Enable PRBS9 pattern prbs_15 4'b0100 Enable PRBS15 pattern prbs_23 4'b1000 Enable PRBS23 pattern prbs_31 4'b0000 Enable PRBS31 pattern sq_wave_1 4'b0001 Enable square wave.
~~PAGE 555~~
UG-01143 2015.05.11 Examples of Enabling the PRBS9 and PRBS31 Pattern Generators Reconfigu‐ Reconfigu‐ ration ration Bit Address (HEX) 0x110 [2:0] Attribute Name ser_mode Related Addresses Attribute Encoding Bit Encoding 6-51 Description sixty_four_bit 3'b011 64-bit mode ten_bit 3'b100 10-bit mode Examples of Enabling the PRBS9 and PRBS31 Pattern Generators Example 6-4: Enable the PRBS9 pattern generator in 10-bit mode 1. 2. 3. 4. 5. 6. Write 0x02 to address 0x000 of the channel.
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~~6-52 UG-01143 2015.05.~~
~~PAGE 557~~
UG-01143 2015.05.11 Examples of Enabling the PRBS Data Checker Reconfigura‐ tion Address (HEX) 0x13F Reconfigura‐ tion Bit [3:0] Attribute Name Related Addresses deser_factor Attribute Encoding Bit Encoding 6-53 Description 10 4'b0001 10-bit mode 64 4'b1110 64-bit mode Examples of Enabling the PRBS Data Checker Example 6-6: Enable the PRBS9 pattern checker in 10-bit mode 1. 2. 3. 4. 5. 6.
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~~PAGE 559~~
~~UG-01143 2015.05.~~
~~PAGE 560~~
6-56 UG-01143 2015.05.11 Timing Closure Recommendations (initial profile and target profiles) during timing driven compilation. These timing arcs make the timing more accurate. When performing a dynamic reconfiguration, you must: • Include constraints to create the extra clocks for all modified or target configurations at the PCS-FPGA fabric interface. Clocks for the base configuration are created by the Quartus II software.
~~PAGE 561~~
UG-01143 2015.05.11 Timing Closure Recommendations 6-57 To enable the Quartus II software to close timing more accurately in this example, the following constraints must be created: • create_clock -name tx_clkout_enh -period 5.12 [get_pins {native_inst| xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst| twentynm_xcvr_native_inst|inst_twentynm_pcs| gen_twentynm_hssi_tx_pld_pcs_interface.
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~~6-58 UG-01143 2015.05.~~
~~PAGE 563~~
Calibration 7 2015.05.11 UG-01143 Subscribe Send Feedback Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Arria 10 transceiver uses hardened Precision Signal Integrity Calibration Engine (PreSICE) to perform calibration routines. Power-up Calibration and User Recalibration are the main types of calibration. • Power-up calibration occurs automatically at device power-up.
~~PAGE 564~~
7-2 Calibration Registers UG-01143 2015.05.11 To check if the calibration process is on, monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy signals. The *_cal_busy signals remain asserted as long as the calibration process is running. Also, the reconfig_waitrequest signal is asserted when the PreSICE controls the internal configuration bus for calibration. The PMA tx_cal_busy and rx_cal_busy are from the same internal node which cannot be separated from the hardware.
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UG-01143 2015.05.11 Avalon-MM Interface Arbitration Registers 7-3 Avalon-MM Interface Arbitration Registers Table 7-1: Avalon-MM Interface Arbitration Registers Bit Offset Address [0] 0x0(51) Description This bit arbitrates the control of Avalon-MM interface. • Set this bit to 0 to control the internal configuration bus by user. • Set this bit to 1 to pass the internal configuration bus control to PreSICE. [1] 0x0 This bit indicates whether or not calibration is done.
~~PAGE 566~~
7-4 UG-01143 2015.05.11 Fractional PLL Calibration Registers PMA Calibration Enable Register Offset Address 0x100 Bit 7 Reserved PMA Calibration Status Register Offset Address 0x101 Reserved Fractional PLL Calibration Registers Table 7-3: Fractional PLL Calibration Registers Bit fPLL Calibration Enable Register Offset Address 0x100 fPLL Calibration Status Register Offset Address 0x101 0 Reserved Reserved 1 fPLL calibration enable. Set 1 to enable calibration.
~~PAGE 567~~
UG-01143 2015.05.11 Power-up Calibration 7-5 Follow these steps to request bus access: 1. Read the offset address 0x0. 2. Keep the value from MSB [7:2] and replace LSB [1:0] with 0x2. 3. Write the new value to offset address 0x0. Follow these steps to return bus access to PreSICE: 1. Read offset address 0x0. 2. Keep the value from MSB [7:2] and replace LSB [1:0] with 0x3. 3. Write the new value to offset address 0x0. Follow these steps to to enable the ATX PLL calibration enable bit: 1.
~~PAGE 568~~
7-6 UG-01143 2015.05.11 Power-up Calibration Figure 7-1: Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels For applications not using PCIe HIP, the power-up calibration starts from Vreg calibration for all banks and channels. Then, calibration starts from bank 1, transceiver 1, sequentially covering all used channels and banks. Vreg Calibration for all transceiver banks and channels Bank ...
~~PAGE 569~~
UG-01143 2015.05.11 User Recalibration 7-7 Figure 7-2: Power-up Calibration Sequence for PCIe HIP and non-PCIe Channels Vreg Calibration for all transceiver banks and channels Bank ... Bank 2 Bank 1 PCIe Channels Calibration fPLL Calibration ATX PLL Calibration CDR / CMU PLL Calibration RX Offset Cancellation Calibration TX termination and Vod Calibration Bank ...
~~PAGE 570~~
7-8 UG-01143 2015.05.11 Calibration Example The proper reset sequence is required after calibration. Altera recommends you use the Altera transceiver reset controller IP which has tx_cal_busy and rx_cal_busy inputs. You need to connect tx_cal_busy and rx_cal_busy from the native PHY outputs to the reset controller inputs in your design. Reset upon calibration is automatically processed when you perform user recalibration. Follow these steps to perform user recalibration: 1.
~~PAGE 571~~
UG-01143 2015.05.11 Fractional PLL Recalibration 7-9 Fractional PLL Recalibration Follow these steps to recalibrate the Fraction PLL (fPLL): 1. 2. 3. 4. 5. 6. 7. 8. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0]. Wait for reconfig_waitrequest to be deasserted (logic low). To calibrate the fPLL, write 0x1 to bit[1] of address 0x100 of the fPLL.
~~PAGE 572~~
7-10 UG-01143 2015.05.11 Recalibration After Transceiver Reference Clock Frequency or Data Rate... Follow these steps to recalibrate the PMA: 1. 2. 3. 4. 5. 6. 7. 8. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0]. Wait for reconfig_waitrequest to be deasserted (logic low). To recalibrate the PMA, write 0x1 to bit[2] or bit[5] of address 0x100 of the PMA.
~~PAGE 573~~
UG-01143 2015.05.11 User Recalibration 7-11 Figure 7-3: Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes fPLL Calibration ATX PLL Calibration CDR / CMU Calibration RX Offset Cancellation Calibration TX Termination and Vod Calibration Calibration Done User Recalibration User recalibration requires access to the internal configuration bus and calibration registers through the Avalon-MM dynamic reconfiguration interface.
~~PAGE 574~~
7-12 Check Calibration Status UG-01143 2015.05.11 The calibration bits for CDR/CMU, TX termination and Vod, and RX Offset Cancellation can be set one time through the internal configuration bus because they are located at the same PMA offset address. The PreSICE executes the calibration in the following order: 1. CDR/CMU 2. RX Offset Cancellation 3.
~~PAGE 575~~
Analog Parameter Settings 8 2015.05.11 UG-01143 Subscribe Send Feedback Transceiver analog parameter settings are used to tune the analog functions in the physical medium attachment (PMA) and the PLL blocks while designing high-speed serial protocol solutions. You can use this feature to compensate for signal losses for high data rate communication. Most transceiver parameters can be set using the Parameter Editor before generating the transceiver PHY IP.
~~PAGE 576~~
8-2 UG-01143 2015.05.11 Analog Parameter Settings List Related Information Quartus II Settings File (.qsf) Describes the commands and options available to modify the assignments in the qsf file. Analog Parameter Settings List The following table lists the analog parameter settings for the transmitter and receiver. The details of each of these settings are in the sections following this table.
~~PAGE 577~~
~~UG-01143 2015.05.~~
~~PAGE 578~~
~~8-4 UG-01143 2015.05.~~
~~PAGE 579~~
UG-01143 2015.05.11 XCVR_A10_RX_TERM_SEL 8-5 Table 8-4: Available Options Value Description SR Chip-to-chip communication LR Backplane communication Note: The maximum data rate supported by transceiver channels depends on the device speed grade, power mode, and the type of channel used. Refer to Arria 10 Device Datasheet for more details. Assign To RX serial data.
~~PAGE 580~~
8-6 UG-01143 2015.05.11 XCVR_VCCR_VCCT_VOLTAGE - RX Syntax set_instance_assignment -name XCVR_A10_RX_TERM_SEL -to XCVR_VCCR_VCCT_VOLTAGE - RX Pin planner or Assignment Editor Name VCCR_GXB and VCCT_GXB voltages Description Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin.
~~PAGE 581~~
UG-01143 2015.05.11 XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 8-7 Arria 10 transceivers support the following two CTLE modes: • High gain mode • High data rate mode. High gain mode is enabled by default for data rates up to 17.4 Gbps. High data rate mode is enabled for data rates higher than 17.4 Gbps. When the RX link is specified as Short Reach (SR), the default value is STG2_GAIN7. For Long Reach (LR), the default is STG1_GAIN7. Note: STGx_GAIN7 is the only valid setting at this time.
~~PAGE 582~~
~~8-8 UG-01143 2015.05.11 XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL Table 8-7: Available Options Value RADP_CTLE_ACGAIN_4S_<0 to 28> Description CTLE AC gain setting <0 to 28> Assign To RX serial data.~~
~~PAGE 583~~
UG-01143 2015.05.11 VGA Settings 8-9 Description Selects between the RX high gain mode or RX high data rate mode for the equalizer. If no assignment is made, then NON_S1_MODE is chosen by default, for data rates up to 17.4 Gbps. For data rates greater than 17.4 Gpbs, S1_MODE is the default value. Table 8-9: Available Options Value NON_S1_MODE Description Selects high gain mode. Selects high gain mode for data rates up to 17.4 Gbps. S1_MODE Selects high data rate mode.
~~PAGE 584~~
8-10 UG-01143 2015.05.11 Decision Feedback Equalizer (DFE) Settings Syntax set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL -to Decision Feedback Equalizer (DFE) Settings The decision feedback equalizer (DFE) amplifies the high frequency component of a signal without amplifying the noise content. The DFE removes the post-cursor Inter Symbol Interference (ISI) of the bits received previously from the current bit and improves the Bit Error Rate (BER).
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UG-01143 2015.05.11 Transmitter General Analog Settings Assignment Pin Planner or Assignment Editor Name Value 8-11 Description XCVR_A10_RX_ ADP_DFE_ FXTAP5 Receiver Decision Feedback Equalizer Fixed Tap Five Coefficient. RADP_DFE_ FXTAP5_<0 to 63> DFE fixed tap 5 Coefficient Setting <0 to 63> XCVR_A10_RX_ ADP_DFE_ FXTAP6 Receiver Decision Feedback Equalizer Fixed Tap Six Coefficient.
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8-12 UG-01143 2015.05.11 XCVR_A10_TX_COMPENSATION_EN Table 8-12: Available Options Value Description SR Chip-to-chip communication LR Backplane communication Note: The maximum data rate supported by transceiver channels depends on the device speed grade, power mode, and the type of transceiver channel. Refer to Arria 10 Device Datasheet for more details. Assign To TX serial data.
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UG-01143 2015.05.11 XCVR_VCCR_VCCT_VOLTAGE - TX Data Rate Value of XCVR_A10_TX_COMPENSATION_EN Others ENABLE/DISABLE 8-13 Assign To TX serial data. Syntax set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN -to XCVR_VCCR_VCCT_VOLTAGE - TX Pin planner or Assignment Editor Name VCCR_GXB and VCCT_GXB voltages Description Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying the intended supply voltages for a GXB I/O pin.
~~PAGE 588~~
8-14 UG-01143 2015.05.11 XCVR_A10_TX_SLEW_RATE_CTRL Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to the fastest rate. Table 8-15: Available Options Value Valid Options SLEW_R0 to SLEW_R7 SLEW_R0 to SLEW_R5 If QSF is not specified, the following table lists the default values.
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UG-01143 2015.05.11 Transmitter Pre-Emphasis Settings 8-15 Transmitter Pre-Emphasis Settings The programable pre-emphasis block in the transmit buffer amplifies the high frequencies in the transmit data to compensate for attenuation in the transmission media. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T Pin planner or Assignment Editor Name Transmitter Pre-Emphasis First Pre-Tap Polarity Description Controls the polarity of the first pre-tap for pre-emphasis. The default value is FIR_PRE_1T_NEG.
~~PAGE 590~~
8-16 UG-01143 2015.05.11 XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP Assign To TX serial data. Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T -to XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP Pin planner or Assignment Editor Name Transmitter Pre-Emphasis First Post-Tap Polarity Description Controls the polarity of the first post-tap for pre-emphasis. The default value is FIR_POST_1T_NEG.
~~PAGE 591~~
UG-01143 2015.05.11 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T Value Description FIR_POST_2T_NEG Negative post-tap 2 8-17 Assign To TX serial data. Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP -to XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T Pin planner or Assignment Editor Name Transmitter Pre-Emphasis First Pre-Tap Magnitude Description Controls the magnitude of the first pre-tap for pre-emphasis. The default value is 0.
~~PAGE 592~~
8-18 UG-01143 2015.05.11 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP Description Controls the magnitude of the second pre-tap for pre-emphasis. The default value is 0. Table 8-22: Available Options Value Description 0–7 Magnitude 0 – 7 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal preemphasis and differential output voltage settings. Assign To TX serial data.
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UG-01143 2015.05.11 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP 8-19 Related Information Arria 10 Pre-Emphasis and Output Swing Settings XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP Pin planner or Assignment Editor Name Transmitter Pre-Emphasis Second Post-Tap Magnitude Description Controls the magnitude of the second post-tap for pre-emphasis. The default value is 0.
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8-20 UG-01143 2015.05.11 Dedicated Reference Clock Settings Table 8-25: Available Options Value Description 0 – 31 Magnitude 0 – 31 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal preemphasis and differential output voltage settings. Assign To TX serial data.
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~~UG-01143 2015.05.11 XCVR_A10_REFCLK_TERM_TRISTATE I/O Standard Value LVPECL TRISTATE_ON/TRISTATE_OFF LVDS TRISTATE_ON/TRISTATE_OFF 8-21 Assign To Reference clock pin.~~
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9 Document Revision History for Current Release 2015.05.11 UG-01143 Subscribe Send Feedback This section provides the revision history for the chapters in this user guide. Chapter Document Version Changes Made Overview 2015.05.11 Changed lower limit of supported data rate from 1.0 Gbps to 611 Mbps Calibration 2015.05.11 Made the following changes: • Changed register offsets globally.
~~PAGE 597~~
9-2 UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version Changes Made • Changed the bit to calibrate the fPLL and changed "Avalon-MM interface" to "internal configuration bus" in the "Fractional PLL Recalibration" section. • Changed "Avalon-MM interface" to "internal configuration bus" in the "CMU or CDR PLL Recalibration" section. • Changed the addresses in the "User Recalibration" section. • Changed the addresses in the "ATX PLL Recalibration" section.
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UG-01143 2015.05.11 Document Revision History for Current Release Chapter Interlaken Document Version 2015.05.11 9-3 Changes Made Made the following changes: • Added available preset variations to the "Interlaken" and "How to Implement Interlaken in Arria 10 Transceivers" sections. • Updated the values for some parameters in the "TX PMA Parameters", "RX PMA Parameters", "Enhanced PCS Parameters", "Interlaken Frame Generator Parameters", and "Interlaken Frame Synchronizer Parameters" tables.
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9-4 UG-01143 2015.05.11 Document Revision History for Current Release Chapter PCI Express (PIPE) Document Version 2015.05.11 Changes Made Made the following changes: • Updated the "Transceiver Channel Datapath for PIPE Gen1/Gen2 Configu‐ rations", "PIPE Gen1/Gen2/Gen3 Configurations", "PCIe Reverse Parallel Loopback Mode Datapath", and "Signals and Ports of Native PHY IP for PIPE" figures. • Updated "Rate Switch" Gen3 features.
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UG-01143 2015.05.11 Document Revision History for Current Release Chapter Other Protocols Document Version 2015.05.11 9-5 Changes Made Made the following changes: • Updated the "Connection Guidelines for a PCS Direct PHY Design" figure. • Updated the "Connection Guidelines for an Enhanced PCS in Low Latency Mode Design" figure. • Updated the description following the "Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion" figure. • Added a Note to the "TX Bit Slip" section.
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9-6 UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version Changes Made • Updated the figure for Transceiver Native PHY IP Core Parameter Editor. • PMA parameters • Updated the PMA parameter categorization in the TX PMA and RX PMA "Equalization" section. • Added parameters Enable tx_pma_ iqtxrx_clkout port and Enable tx_seriallpbken port in "TX PMA Optional Ports" table. • Added parameters Enable rx_pma_ iqtxrx_clkout port in "RX PMA Optional Ports" table.
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UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version 9-7 Changes Made • Enhanced PCS Parameters • Removed the Enable rx_enh_fifo_ cnt port and Enable tx_enh_ fifo_cnt port parameters. • Removed description of parameter TX FIFO Mode for Register Mode in "Enhanced PCS TX FIFO Parameters" table. • Added Error marking type parameter in the "Gearbox Parameters" table.
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9-8 UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version Changes Made • Dynamic Reconfiguration Parameters • Changed the table name from "Embedded Debug" to "Optional Reconfiguration Logic". • Deleted the parameter Enable Embedded Debug from "Optional Reconfiguration Logic" table. • Added the parameter Enable ODI acceleration logic in "Optional Reconfiguration Logic" table. • Added a new section "Configuration Profiles".
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UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version 9-9 Changes Made • Enhanced PCS Ports • Deleted ports tx_enh_fifo_cnt and rx_enh_fifo_cnt from "Enhanced PCS TX and RX FIFO" tables. • Added "KR-FEC" table. • Updated table name from "Bitslip" to "Gearbox". • Updated bit offset, functionality and description for ports tx_control and rx_control in tables "Bit Encodings for Interlaken with Enable Simplified Interfaced ON" and "Enable Simplified Interfaced OFF".
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9-10 UG-01143 2015.05.11 Document Revision History for Current Release Chapter PMA Architecture Document Version 2015.05.11 Changes Made Made the following changes: • Updated link to XCVR_A10_RX_ TERM_SEL in the "Transmitter Buffer". • Updated ODI vertical steps to 63 (0 and +/-32) in the "Receiver Buffer". • Updated CTLE section for adaptation modes. Moved CTLE in the "How to Enable CTLE and DFE" section. • Updated VGA section for adaptation modes. • Updated DFE section for adaptation modes.
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UG-01143 2015.05.11 Document Revision History for Current Release Chapter Document Version Reconfiguration Interface 2015.05.11 and Dynamic Reconfigura‐ tion Changes Made Made the following changes: • Completely revised, updated, and reorganized the chapter. • Added the following new sections: • • • • • • • • Analog Parameter Settings 2015.05.
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9-12 UG-01143 2015.05.11 Document Revision History for Previous Releases Document Revision History for Previous Releases Table 9-1: Document Revision History Chapter Document Version Arria 10 Transceiver PHY Overview 2014.12.15 Using the Arria 10 Transceiver Native PHY IP Core 2014.12.15 Altera Corporation Changes Made Made the following changes: • Added statement that a 125-Mbps data rate is possible with oversampling in the "Arria 10 Transceiver PHY Overview" section.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Interlaken Document Version 2014.12.15 9-13 Changes Made Made the following changes to the parameter tables: • Added another value to the "TX channel bonding mode" parameter in the "TX PMA Parameters" table. • Added values to the "PCS TX channel bonding master" and "Actual PCS TX channel bonding master" parameters in the "TX PMA Parameters" table.
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9-14 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter 10GBASE-KR PHY IP with FEC Option Document Version 2014.12.15 Changes Made Made the following changes: • Changed the "10GBASE-KR PHY IP Core Block Diagram" figure to activate the Standard TX PCS, Standard RX PCS, and GbE PCS blocks. • Added a note to the "10GBASE-KR Functional Description" section. • Added new parameters to the "General Options" table.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter XAUI PHY IP Core Document Version 2014.12.15 9-15 Changes Made Made the following changes: • Added a PMA width requirement in the "Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration" section. • Changed the figure description for the "Transceiver Clocking for XAUI Configuration" figure. • Changed the note in the "Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration" section.
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9-16 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Changes Made PCI Express 2014.12.15 • Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection. • Updated the Rate Switch Change figure. • Updated the Bit Mappings When the Simplified Interface Is Disabledtable. • Updated the figures in How to Place Channels for PIPE Configurations. • Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA table.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Other Protocols Document Version 2014.12.15 9-17 Changes Made Made the following changes: Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS • Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity Inversion".
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9-18 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Resetting Transceiver 2014.12.15 Channels Arria 10 Transceiver PHY Architecture 2014.12.15 Changes Made Made the following changes: • Updated the "Transmitter Reset Sequence After Power-Up" and "Transmitter Reset Sequence During Device Operation" figures. • Improved formatting in the "Transceiver PHY Reset Controller IP Core Top-Level Signals" figure.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Reconfiguration Interface and Dynamic Reconfigu‐ ration Document Version 2014.12.15 Changes Made Made the following changes: • Re-organized the chapter outline to better match the reconfiguration flow. • Updated the introduction section of the chapter to better explain dynamic reconfiguration use cases.
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9-20 UG-01143 2015.05.11 Document Revision History for Previous Releases Table 9-2: Document Revision History Chapter Document Version Changes Made Ethernet 2014.10.08 Changed the frequency for mgmt_clk in the "Avalon-MM Interface Signals" table for 10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core. Other Protocols 2014.10.08 Removed an erroneous note regarding Quartus II software legality check restrictions. Reconfiguration 2014.10.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Arria 10 Transceiver Protocols and PHY IP Support Document Version 2014.08.15 Document Revision History for Current Release Send Feedback 9-21 Changes Made Made the following changes: • Updated table "Arria 10 Transceiver Protcols and PHY IP Support" • Removed SFIS and 10G SDI from the table. • Updated Protocol Preset, Transceiver Configuration Rule, and PCS Support for protocols in the table.
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9-22 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Using the Arria 10 2014.08.15 Transceiver Native PHY IP Changes Made Made the following changes: • Updated references of MegaWizard Plug-In Manager to IP Catalog and Parameter Editor. • Added PCS Direct block in figure "Transceiver Native PHY IP Top Level Interfaces and Functional Blocks". • Updated figure "Transceiver Native PHY IP GUI" for 14.0A10 release IP GUI.
~~PAGE 618~~
UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Interlaken Document Version 2014.08.15 9-23 Changes Made Made the following changes: • Changed parameter name in the "Signals and Ports of Native PHY IP for Interlaken" figure from tx_bonding_clock to tx_ bonding_clock[5:0]. • Updated tables in the "Native PHY IP Parameter Settings for Interlaken" section: • Added new tables: "10GBASE-R BER Checker Parameters", "KR-FEC Parameters".
~~PAGE 619~~
9-24 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Changes Made • Specified the target BER of 10-12 in the 10GBASE-KR PHY IP Core section. • Removed the "Top Level Modules of the 1G/10GbE PHY MegaCore Function" figure. • Removed the 10GBASE-KR PHY with 1588 variant from the "10GBASE-KR PHY Performance and Resource Utilization" table. This is not supported. • Replaced the "10GBASE-KR PHY IP Block Diagram" figure. • Added the Auto Negotiation, IEEE 802.
~~PAGE 620~~
UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version 9-25 Changes Made • Updated the list of signals in the "Dynamic Reconfiguration Interface Signals" table. • Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register Definitions" table. • Updated the 0x482 registers in the "PCS Registers" table. • Updated and removed some addresses in the "PMA Registers" table. • Added the Speed Change Summary section.
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9-26 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter PCI Express Document Version 2014.08.15 Changes Made Made the following changes: • Added a new topic Pipe link equalization for Gen 3 data rate. • Changed "MegaWizard Plugin Manager" to "Parameter Editor"/ "IP Catalog" in the How to Connect TX PLLs for PIPE Gen1, Gen2 and Gen3 Mode section.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Other Protocols Document Version 2014.08.15 9-27 Changes Made Made the following changes: • Changed references from MegaWizard to IP Catalog or Parameters Editor. • Using the Basic and Basic with KR FEC Configurations of Enhanced PCS • Updated the "Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) Configuration" figure and added footnote 3.
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9-28 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Changes Made • Changed the maximum data rate for GT channels to 28.3 Gbps. • Changed figure "Arria 10 PLLs and Clock Networks" to indicate channel 0,1,3, and 5 have only the CDR PLL. • Updated figure "x1 Clock Lines" to indicate that the channel PLL of channel 1 and channel 4 can be used as CMU PLL or as a CDR.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version 9-29 Changes Made • Updated Using PLLs and Clock Networks section • Changed MegaWizard references to IP Catalog and Parameter Editor. • Updated the valid configurations for PLL IP and Native PHY IP per 14.0A10 release change. • Removed Table "xN Clock Network Data Rate Restrictions". • Updated the chapter to indicate Arria 10 transceivers support to fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading.
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9-30 UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Arria 10 Transceiver PHY Architecture Document Version 2014.08.15 Changes Made Made the following changes • Arria 10 PMA Architecture • Added 2nd post-tap and pre-tap Pre-Emphasis signals . • Updated DFE and CTLE modes of operation and Use Models. • Added new sections on How to Enable CTLE and How to Enable DFE. • Changed max data rate for GT channels to 28.3 Gbps in the Receiver Buffer CTLE section.
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UG-01143 2015.05.11 Document Revision History for Previous Releases Chapter Document Version Reconfiguration 2014.08.15 Interface and Dynamic Reconfi‐ guration Changes Made Made the following changes: • Updated MegaWizard references to IP Catalog or Parameter Editor. • Updated table "Avalon Interface Parameters" • • • • • • Analog Parameter Settings Date December 2013 2014.08.15 Document Revision History for Current Release Send Feedback • Added description for Altera Debug Master Endpoint.