User guide

Parameters Value
Number of word alignment patterns to achieve
sync
3
(38)
Number of invalid data words to lose sync 3
(39)
Number of valid data words to decrement error
count
3
(40)
Enable fast sync status reporting for deterministic
latency SM
On / Off
Enable rx_std_wa_patternalign port
On / Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable rx_bitslip port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
All options under Bit Reversal and Polarity
Inversion
Off
All options under PCIe Ports Off
Table 2-172: Dynamic Reconfiguration
Parameter Value
Enable dynamic reconfiguration Off
Share reconfiguration interface Off
Enable Altera Debug Master Endpoint Off
Enable embedded debug Off
Enable capability registers Off
Set user-defined IP identifier 0
Enable control and status registers Off
Enable prbs soft accumulators Off
Configuration file prefix altera_xcvr_native_a10
Generate SystemVerilog package file Off
(38)
These are unused when the transceiver PHY is in CPRI mode
(39)
These are unused when the transceiver PHY is in CPRI mode
(40)
These are unused when the transceiver PHY is in CPRI mode
2-278
Native PHY IP Parameter Settings for CPRI
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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