User guide
Figure 2-103: Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with KR FEC
Configurations
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
rx_parallel_data[127:0]
tx_control[17:0] tx_control[17:0]
tx_digital_resettx_digital_reset
tx_parallel_data[127:0]
reconfig_clk
reconfig_avmm
reconfig_reset
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
RX PMA
TX Enhanced PCS
RX Enhanced PCS
Deserializer
Clock
Generation
Block
rx_cdr_refclk0
CDR
rx_clkout
rx_coreclkin
rx_clkout
rx_coreclkin
rx_analog_reset
tx_analog_reset
rx_digital_resetrx_digital_reset
rx_parallel_data[127:0]
rx_control[19:0]
5.
Configure and instantiate the PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use the Altera
Transceiver PHY Reset Controller IP.
7. Connect the Native PHY IP to the PLL IP and the reset controller.
2-282
How to Implement the Basic (Enhanced PCS) and Basic with KR FEC...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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