User guide

Figure 2-104: Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
Reset
Controller
Arria 10 Transceiver
Native PHY
Design
Testbench
32-bit data
(32:32
gearbox ratio)
PLL IP
Figure 2-105: Connection Guidelines for a Basic with KR FEC Transceiver Design
Design
Testbench
64d + 8c
PLL IP
Reset
Controller
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
Arria 10 Enhanced PCS Architecture on page 5-18
For more information about Enhanced PCS architecture
Arria 10 PMA Architecture on page 5-1
For more information about PMA architecture
Using PLLs and Clock Networks on page 3-49
For more information about implementing PLLs and clocks
PLLs on page 3-3
PLL architecture and implementation details
Resetting Transceiver Channels on page 4-1
Reset controller general information and implementation details
Enhanced PCS Ports on page 2-54
For detailed information about the available ports in the Basic protocol.
UG-01143
2015.05.11
How to Implement the Basic (Enhanced PCS) and Basic with KR FEC...
2-283
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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