User guide

Table 2-177: Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
Note: Basic with KR FEC allows 64 only
FPGA fabric/Enhanced PCS interface
width
32, 40, 50, 64, 66, 67
Note: Basic with KR FEC allows 66 only
Enable 'Enhanced PCS' low latency
mode
On / Off
Enable RX/TX FIFO double width
mode
On / Off
TX FIFO mode Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced and Basic Enhanced with
KRFEC are valid.
TX FIFO partially full threshold 10, 11, 12, 13, 14, 15
TX FIFO partially empty threshold 1, 2, 3, 4, 5
Enable tx_enh_fifo_full port
On / Off
Enable tx_enh_fifo_pfull port
On / Off
Enable tx_enh_fifo_empty port
On / Off
Enable tx_enh_fifo_pempty port
On / Off
RX FIFO mode Phase Compensation, Register, Basic
RX FIFO partially full threshold 0 to 31
RX FIFO partially empty threshold 0 to 31
Enable RX FIFO alignment word
deletion (Interlaken)
On / Off
Enable RX FIFO control word deletion
(Interlaken)
On / Off
Enable rx_enh_data_valid port
On / Off
Enable rx_enh_fifo_full port
On / Off
2-286
Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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