User guide

Parameter Range
Enable rx_enh_fifo_pfull port
On / Off
Enable rx_enh_fifo_empty port
On / Off
Enable rx_enh_fifo_pempty port
On / Off
Enable rx_enh_fifo_del port
(10GBASE-R)
On / Off
Enable rx_enh_fifo_insert port
(10GBASE-R)
On / Off
Enable rx_enh_fifo_rd_en port
(Interlaken)
On / Off
Enable rx_enh_fifo_align_val port
(Interlaken)
On / Off
Enable rx_enh_fifo_align_cir port
(Interlaken)
On / Off
Enable TX 64b/66b encoder
On / Off
Enable RX 64b/66b decoder
On / Off
Enable TX sync header error insertion
On / Off
Enable RX block synchronizer On / Off
Enable rx_enh_blk_lock port
On / Off
Enable TX data bitslip On / Off
Enable TX data polarity inversion On / Off
Enable RX data bitslip On / Off
Enable RX data polarity inversion On / Off
Enable tx_enh_bitslip port
On / Off
Enable rx_bitslip port
On / Off
Enable RX KR-FEC error marking
On / Off
Error marking type
10G, 40G
Enable KR-FEC TX error insertion
On / Off
KR-FEC TX error insertion spacing
On / Off
UG-01143
2015.05.11
Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic...
2-287
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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