User guide

Chapter 1: About This IP 1–5
Unsupported Features
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Unsupported Features
The DDR3 SDRAM Controller with ALTMEMPHY IP does not support the following
features:
■ Timing simulation.
■ Partial burst and unaligned burst in ECC and non-ECC mode when DM pins are
disabled.
MegaCore Verification
Altera performs extensive random, directed tests with functional test coverage using
industry-standard Denali models to ensure the functionality of the DDR3 SDRAM
Controller with ALTMEMPHY IP.
Resource Utilization
The following sections show the resource utilization data for the ALTMEMPHY
megafunction, and the DDR3 high-performance controllers (HPC and HPC II).
ALTMEMPHY Megafunction
Table 1–4 and Table 1–5 show the typical size of the ALTMEMPHY megafunction with
the AFI in the Quartus II software version 10.0 for the following devices:
■ Arria II GX (EP2AGX260FF35C4) devices
■ Stratix III (EP3SL110F1152C2) devices
■ Stratix IV (EP4SGX230HF35C2) devices
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulator
vv
Notes to Table 1–3:
(1) HPC II supports additive latency values greater or equal to t
RCD
-1, in clock cycle unit (t
CK
).
(2) This feature is not supported with DDR3 SDRAM with leveling
.
Table 1–3. DDR3 SDRAM HPC and HPC II Features (Part 2 of 2)
Features
Controller Architecture
HPC HPC II