User guide

Chapter 9: Timing Diagrams 9–5
DDR3 High-Performance Controllers
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The following sequence corresponds with the numbered items in Figure 9–3:
1. The local read request signal is asserted.
2. The controller accepts the request, the
local_ready signal is asserted.
3. The controller asserts the
ctl_doing_rd to tell the PHY how many clock cycles of
read data to expect.
4. The read command (RD) on the command bus.
5. The
mem_dqs signal has the read data from the controller.
6. These are the data to the controller with the valid signal.
7. The controller returns the valid read data to the user logic by asserting the
local_rdata_valid signal when there is valid local read data.