User guide

9–24 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The following sequence corresponds with the numbered items in Figure 9–13:
1. The user logic asserts a
local_write_req signal with a size of 2 and an address of
0×0000F1C .
2. The controller issues the necessary memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
3. The controller asserts the
afi_wdata_valid signal to indicate to the ALTMEMPHY
megafunction that valid write data and write data masks are present on the inputs
to the ALTMEMPHY megafunction.
4. The controller asserts the
afi_dqs_burst signals to control the timing of the DQS
signal that the ALTMEMPHY megafunction issues to the memory.
5. The ALTMEMPHY megafunction issues the write command, and sends the write
data and write DQS to the memory.
6. For transactions with a local size of two, the
local_write_req and local_ready
signals must be high for two clock cycles so that all the write data can be
transferred to the controller.
Half-Rate Write Operation (Merging Writes)
Figure 9–14. Write Operation for HPC II—Merging Writes
local_address[25:0]
Local Interface
local_size[4:0]
local_ready
local_burstbegin
local_be[3:0]
local_write_req
local_wdata[31:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_wdata[31:0]
afi_wdata_valid[1:0]
mem_cke
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
00000010000000 0000002 0000003
22222222 3333333300000000 00000000
0000000 4001000 0000000 4021008 0000000
F B F B F B F
ACT NOP
NOPACT
NOP NOPWR WR
0
00000000 22222222 33333333 00000000
3 0 3
1000 0000 1008 0000
WR NOP WR NOP
00 22 33 00
phy_clk
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