User guide

Chapter 5: Functional Description—ALTMEMPHY 5–17
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The phase-shift inputs on the PLL perform the PLL reconfiguration. The PLL
reconfiguration megafunction is not required.
Reset Management
Figure 5–8 and Figure 5–9 show the main features of the reset management block for
the DDR3 SDRAM PHY. You can use the
pll_ref_clk input to feed the optional
reset_request_n edge detect and reset counter module. However, this requires the
pll_ref_clk signal to use a global clock network resource.
There is a unique reset metastability protection circuit for the clock divider circuit
because the
phy_clk domain reset metastability protection registers have fan-in from
the
soft_reset_n input so these registers cannot be used.
ac_clk_1x C6
Set in the
GUI
Half-Rate Regional Address and command clock.
Notes to Table 5–2:
(1) In full-rate designs a _1x clock may run at full-rate clock rate.
(2) This clock should be of the same clock network clock as the
resync _ clk _ 1x clock.
Table 5–2. DDR3 SDRAM Clocking Stratix IV and Stratix III Devices (Part 2 of 2)
Clock Name (1)
Postscale
Counter
Phase
(Degrees)
Clock
Rate
Clock
Network
Type
Notes
Figure 5–7. ALTMEMPHY Reset Management Block for Arria II GX Devices
PLL
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
soft_reset_n
global_reset_n
pll_ref_clk
phy_clk_out
reset_request_n
phy_internal_reset_n
areset
(active HIGH)
pll_reconfig_reset_ams_n
pll_reprogram_request_long_pulse
seq_pll_start_reconfig
pll_reconfig_
reset_
ams_n_r
pll_
reprogram_
request
refclk
scan_clk
phaseupdown
phasestep
c0
locked
reset_master_ams
global_pre_clear
Reset
Pipes
PHY resets
pll_reset
pll_locked
pll_new_dir
Optional
reset_request_n
edge detect and
reset counter
Another
system
clock
clk_divider_reset_n
clk
Divider
Circuit
phy_clk
scan_clk
reset_n
clk_div_reset_ams_n
clk_div_reset_ams_n_r
pll_reconfig_reset_n
global_or_soft_reset_n
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D