User guide
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1. About This IP
The Altera
®
 DDR3 SDRAM Controller with ALTMEMPHY IP provides simplified 
interfaces to industry-standard DDR3 SDRAM. The ALTMEMPHY megafunction is 
an interface between a memory controller and the memory devices, and performs 
read and write operations to the memory. The DDR3 SDRAM Controller with 
ALTMEMPHY IP works in conjunction with the Altera ALTMEMPHY megafunction. 
The DDR3 SDRAM Controller with ALTMEMPHY IP and ALTMEMPHY 
megafunction support DDR3 SDRAM interfaces in half-rate mode. The DDR3 
SDRAM Controller with ALTMEMPHY IP offers two controller architectures: the 
high-performance controller (HPC) and the high-performance controller II (HPC II). 
HPC II provides higher efficiency and more advanced features. 
1 DDR3 SDRAM high-performance controller denotes both HPC and HPC II unless 
indicated otherwise.
Figure 1–1 on page 1–1 shows a system-level diagram including the example top-level 
file that the DDR3 SDRAM Controller with ALTMEMPHY IP creates for you. 
The MegaWizard
™ Plug-In Manager generates an example top-level file, consisting of 
an example driver, and your DDR3 SDRAM high-performance controller custom 
variation. The controller instantiates an instance of the ALTMEMPHY megafunction 
which in turn instantiates a phase-locked loop (PLL) and DLL. You can also 
instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL 
between multiple instances of the ALTMEMPHY megafunction. You cannot share a 
PLL between multiple instances of the ALTMEMPHY megafunction, but you may 
share some of the PLL clock outputs between these multiple instances.
The example top-level file is a fully-functional design that you can simulate, 
synthesize, and use in hardware. The example driver is a self-test module that issues 
read and write commands to the controller and checks the read data to produce the 
pass or fail, and test complete signals. 
Figure 1–1. System-Level Diagram
Note to Figure 1–1: 
(1) When you choose Instantiate DLL Externally, delay-locked loop (DLL) is instantiated outside the ALTMEMPHY 
megafunction.
Pass or Fail
External
Memory
Device
ALTMEMPHY
High-
Performance
Controller
Example
Driver
PLL
Example Top-Level File
DLL
(1)










