User guide

5–28 Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
dqs_delay_ctrl_impor
t
Input
DQS_DELA
Y_CTL_WI
DTH
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the
dqs_delay_ctrl_export port
on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY instance.
dqs_offset_delay_ctr
l_ width
Input
DQS_DELA
Y_CTL_WI
DTH
Connects to the DQS delay logic when dll_import_export is set
to
IMPORT . Only connect if you are using a DLL offset, which can
otherwise be tied to zero. If you are using a DLL offset, connect this
input to the
offset_ctrl_out output of the dll_offset_ctrl
block.
dll_reference_ clk Output 1
Reference clock to feed to an externally instantiated DLL. This clock
is typically from one of the PHY PLL outputs.
User-Mode Calibration OCT Control Signals
oct_ctl_rs_value Input 14
OCT RS value port for use with ALT_OCT megafunction if you want
to use OCT with user-mode calibration.
oct_ctl_rt_value Input 14
OCT RT value port for use with ALT_OCT megafunction if you want to
use OCT with user-mode calibration.
Debug Interface Signals (Note 1), (Note 2)
dbg_clk Input 1 Debug interface clock.
dbg_reset_n Input 1 Debug interface reset.
dbg_addr Input
DBG_A_WI
DTH
Address input.
dgb_wr Input 1 Write request.
dbg_rd Input 1 Read request.
dbg_cs Input 1 Chip select.
dbg_wr_data Input 32 Debug interface write data.
dbg_rd_data Output 32 Debug interface read data.
dbg_waitrequest Output 1 Wait signal.
PLL Reconfiguration Signals—Stratix III and Stratix IV Devices
pll_reconfig_enable Input 1
This signal enables the PLL reconfiguration I/O, and is used if the
user requires some custom PLL phase reconfiguration. It should
otherwise be tied low.
pll_phasecountersele
ct
Input 4
When
pll_reconfig_enable is asserted, this input is directly
connected to the PLL's
phasecounterselect input. Otherwise this
input has no effect.
pll_phaseupdown Input 1
When
pll_reconfig_enable is asserted, this input is directly
connected to the PLL's
phaseupdown input. Otherwise this input has
no effect.
pll_phasestep Input 1
When
pll_reconfig_enable is asserted, this input is directly
connected to the PLL's
phasestep input. Otherwise this input has
no effect.
pll_phase_done Output 1 Directly connected to the PLL's phase_done output.
I/O Delay Chain Signals—Stratix III, HardCopy III, and HardCopy IV Devices
Table 5–5. Other Interface Signals (Part 2 of 4)
Signal Name Type Width Description