User guide

Chapter 6: Functional Description—High-Performance Controller 6–3
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Write Data Tracking Logic
The write data tracking logic keeps track of the number of write data beats in the FIFO
buffer. In native interface mode, this logic manages how much more data to request
from the user logic and issues the
local_wdata_req signal.
Main State Machine
The main state machine decides what DDR commands to issue based on inputs from
the command FIFO buffer, the bank management logic, and the timer logic.
Bank Management Logic
The bank management logic keeps track the current state of each bank. It can keep a
row open in every bank in your memory system. The state machine uses the
information provided by this logic to decide whether it needs to issue bank
management commands before it reads or writes to the bank. The controller always
leaves the bank open unless the user requests an auto-precharge read or write. The
periodic refresh process also causes all the banks to be closed.
Timer Logic
The timer logic tracks whether the required minimum number of clock cycles has
passed since the last relevant command was issued. For example, the timer logic
records how many cycles have elapsed since the last activate command so that the
state machine knows it is safe to issue a read or write command (t
RCD
). The timer
logic also counts the number of clock cycles since the last periodic refresh command
and sends a high priority alert to the state machine if the number of clock cycles has
expired.
Initialization State Machine
The initialization state machine issues the appropriate sequence of command to
initialize the memory devices. It is specific to DDR3 as each memory type requires a
different sequence of initialization commands.
With the AFI, the ALTMEMPHY megafunction initializes the memory, otherwise the
controller is responsible for initializing the memory.
Address and Command Decode
When the state machine wants to issue a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these into the
DDR-specific RAS, CAS, and WE commands.