Specifications

ManualsBrandsAltera ManualsConsumer electronicsStratix GX

101 Innovation Drive

San Jose, CA 95134

www.altera.com

MNL-01063-1.5

Reference Manual

Stratix V GX FPGA Development Board

Feedback Subscribe

Summary of content (76 pages)

PAGE 1
Stratix V GX FPGA Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01063-1.
PAGE 2
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
PAGE 3
Contents Chapter 1. Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
iv ContentsContents Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57 Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59 Temperature Sense .
PAGE 5
1. Overview This document describes the hardware features of the Stratix® V GX FPGA development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board. General Description The Stratix V GX FPGA development board provides a hardware platform for developing and prototyping high-performance and high-bandwidth application designs.
PAGE 6
1–2 Chapter 1: Overview Board Component Blocks Board Component Blocks The board features the following major component blocks: ■ ■ ■ ■ ■ Altera Stratix V FPGA (5SGXEA7K2F40C2N) in the 1517-pin FineLine BGA Package ■ 622,000 LEs ■ 234,720 adaptive logic modules (ALMs) ■ 50-Mbits (Mb) embedded memory ■ 36 transceivers (12.
PAGE 7
Chapter 1: Overview Board Component Blocks 1–3 ■ ■ ■ ■ ■ ■ October 2014 Communication Ports ■ PCI Express (PCIe) x8 edge connector ■ Two HSMC ports ■ One universal HSMC port A ■ One DQS-type HSMC port B ■ SMB for SDI input and output ■ QSFP ■ USB 2.
PAGE 8
1–4 Chapter 1: Overview Development Board Block Diagram Development Board Block Diagram Figure 1–1 shows the block diagram of the Stratix V GX FPGA Development Board. Figure 1–1. Stratix V GX FPGA Development Board Block Diagram XCVR x6 CLKOUT x3 CLKIN x3 CLKIN x3 JTAG Chain x80 Port B XCVR x8 Port A CLKOUT x3 DQS/Single-Ended On-Board USB- Blaster II and USB Interface x80 Micro-USB 2.0 LVDS/Single-Ended x19 USB Interface QSFP x72 1152 MB DDR3 x18 4.
PAGE 9
2. Board Components This chapter introduces all the important components on the Stratix V GX FPGA Development Board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board. 1 A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Stratix V GX FPGA development kit documents directory.
PAGE 10
2–2 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Stratix V GX FPGA development board, including an annotated board image and component descriptions. Figure 2–1 provides an overview of the development board features. Figure 2–1.
PAGE 11
Chapter 2: Board Components Board Overview 2–3 Table 2–1. Stratix V GX FPGA Development Board Components (Part 2 of 4) Board Reference Type Description SW6 PCI Express DIP switch Controls the PCI Express lane width by connecting prsnt pins together on the PCI Express edge connector. This switch is located at the back of the board. S3 Program select push button Toggles the program LEDs which selects the program image that loads from flash memory to the FPGA.
PAGE 12
2–4 Chapter 2: Board Components Board Overview Table 2–1. Stratix V GX FPGA Development Board Components (Part 3 of 4) Board Reference Type Description X3 50 M oscillator 50.000-MHz crystal oscillator for general purpose logic. J13, J14 Clock input SMAs Drives LVPECL-compatible clock inputs into the clock multiplexer buffer. U4 100 M oscillator 100-MHz crystal oscillator for the MAX V CPLD System Controller.
PAGE 13
Chapter 2: Board Components Featured Device: Stratix V GX FPGA 2–5 Table 2–1. Stratix V GX FPGA Development Board Components (Part 4 of 4) Board Reference Type Description Power Supply J18 PCI Express edge connector Interfaces to a PCI Express root port such as an appropriate PC motherboard. J4 DC input jack Accepts a 19-V DC power supply. SW2 Power switch Switch to power on or off the board when power is supplied from the DC input jack.
PAGE 14
2–6 Chapter 2: Board Components MAX V CPLD System Controller Table 2–4. Stratix V GX FPGA Pin Count and Usage (Part 2 of 2) Function I/O Standard I/O Count Special Pins 1.8-V CMOS 68 — 2.5-V CMOS + XCVR 43 1 REFCLK Flash PCI Express ×8 HSMC Port A 2.5-V CMOS + LVDS + XCVR 118 1 REFCLK HSMC Port B 2.5-V CMOS + DQS + XCVR 104 1 REFCLK 2.5-V CMOS + LVDS 8 — 1.5-V CMOS 18 — 3.3-V CMOS 1 — SDI Video 2.5-V CMOS + XCVR 8 1 REFCLK QSFP 2.5-V CMOS + XCVR 23 1 REFCLK Buttons 1.
PAGE 15
Chapter 2: Board Components MAX V CPLD System Controller 2–7 Figure 2–2 illustrates the MAX V CPLD System Controller's functionality and external circuit connections as a block diagram. Figure 2–2.
PAGE 16
2–8 Chapter 2: Board Components MAX V CPLD System Controller Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 2 of 6) Schematic Signal Name MAX V CPLD Stratix V GX FPGA Pin Number Pin Number I/O Standard Description FACTORY_STATUS N12 — 1.8-V On-Board USB-Blaster II FACTORY command status FLASH_ADVn N7 AP7 1.8-V FM bus flash memory address valid FLASH_CEn0 R5 AV14 1.8-V FM bus flash memory chip enable 0 FLASH_CEn1 M7 AW13 1.
PAGE 17
Chapter 2: Board Components MAX V CPLD System Controller 2–9 Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 3 of 6) Schematic Signal Name MAX V CPLD Stratix V GX FPGA Pin Number Pin Number I/O Standard Description FM_D2 K16 AD20 1.8-V FM data bus FM_D3 K13 AG21 1.8-V FM data bus FM_D4 K15 AH21 1.8-V FM data bus FM_D5 K14 AE21 1.8-V FM data bus FM_D6 L16 AE20 1.8-V FM data bus FM_D7 L11 AL22 1.8-V FM data bus FM_D8 L15 AK21 1.
PAGE 18
2–10 Chapter 2: Board Components MAX V CPLD System Controller Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 4 of 6) Schematic Signal Name MAX V CPLD Stratix V GX FPGA Pin Number Pin Number I/O Standard Description FPGA_CONFIG_D8 F3 AT32 2.5-V FPGA configuration data FPGA_CONFIG_D9 E1 AR31 2.5-V FPGA configuration data FPGA_CONFIG_D10 F4 AP31 2.5-V FPGA configuration data FPGA_CONFIG_D11 F2 AW34 2.5-V FPGA configuration data FPGA_CONFIG_D12 F1 AV34 2.
PAGE 19
Chapter 2: Board Components MAX V CPLD System Controller 2–11 Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 5 of 6) Schematic Signal Name MAX V CPLD Stratix V GX FPGA Pin Number Pin Number I/O Standard Description MAX5_BEN1 R11 T31 1.8-V MAX V byte enable 1 MAX5_BEN2 T12 N33 1.8-V MAX V byte enable 2 MAX5_BEN3 N11 M33 1.8-V MAX V byte enable 3 MAX5_CLK T11 E34 1.8-V MAX V clock MAX5_CSN R10 B32 1.8-V MAX V chip select MAX5_OEN M10 A32 1.
PAGE 20
2–12 Chapter 2: Board Components Configuration, Status, and Setup Elements Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 6 of 6) Schematic Signal Name MAX V CPLD Stratix V GX FPGA Pin Number Pin Number I/O Standard Description SI571_EN D4 — 2.5-V Si571 programmable VCXO enable TSENSE_ALERTn B5 — 2.5-V Temperature monitor alert Table 2–6 lists the MAX V CPLD System Controller component reference and manufacturing information. Table 2–6.
PAGE 21
Chapter 2: Board Components Configuration, Status, and Setup Elements 2–13 MAX II CPLD EPM570GM100 The MAX II CPLD is dedicated to the on-board USB-Blaster II functionality. The CPLD connects to the CY7C68013A USB 2.0 PHY device on one side and drives the JTAG and System Console direct USB signals out the other side through the general purpose I/O (GPIO) pins. Table 2–7 lists the I/O signals present on the MAX II CPLD EPM570GM100. Table 2–7.
PAGE 22
2–14 Chapter 2: Board Components Configuration, Status, and Setup Elements JTAG Chain The on-board USB-Blaster II is automatically disabled when you connect an external USB-Blaster to the JTAG chain or when you enable JTAG from the PCI Express edge connector. Figure 2–3 illustrates the JTAG chain. Figure 2–3.
PAGE 23
Chapter 2: Board Components Configuration, Status, and Setup Elements 1 2–15 By default, the on-board USB-Blaster II clocks TCK at 24 MHz. For the on-board USB-Blaster II to function correctly, you must set the Quartus II clock constraint on the internal_tck input signal to 24 MHz. System Console USB Interface The System Console USB interface is a fast parallel interface. Together with the soft logic supplied by Altera, this interface provides a System Console master for debug access.
PAGE 24
2–16 Chapter 2: Board Components Configuration, Status, and Setup Elements The secondary method is to use the pre-built PFL design included in the development kit. The development board implements the Altera PFL megafunction for flash programming. The PFL megafunction is a block of logic that is programmed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible flash device.
PAGE 25
Chapter 2: Board Components Configuration, Status, and Setup Elements 2–17 Figure 2–4 shows the PFL configuration. Figure 2–4. PFL Configuration 2.5 V 2.5 V 56.2 Ω 2.5 V 2.5 V 56.2 Ω 10 kΩ MAX V CPLD System Controller 10 kΩ 2.5 V 50 MHz 1 kΩ 100 MHz ERROR LOAD FACTORY DIP Switch FPGA_INIT_DONE USB-BLASTER FPGA_nSTATUS FPGA_nCONFIG FPGA_CONF_DONE CLK_SEL CLK_ENABLE CONF_DONE USER_PGM FPGA_DATA [0] USB_SELECT FPGA_DCLK MAX_RESETn 2.5 V PGM_CONFIG 56.
PAGE 26
2–18 Chapter 2: Board Components Configuration, Status, and Setup Elements f For more information on the following topics, refer to the respective documents: ■ Board Update Portal and PFL Design, refer to the Stratix V GX FPGA Development Kit User Guide. ■ PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the Quartus II Software.
PAGE 27
Chapter 2: Board Components Configuration, Status, and Setup Elements 2–19 Table 2–10. Board-Specific LEDs (Part 2 of 2) Board Reference Schematic Signal Name LED Name The sequence displayed determines if the factory design or a user design is used to configure the FPGA from flash when you press the PGM_LOAD push button. Refer to Table 2–9 for the push button configuration settings. PGM_LED0 D4, D5, D6 PGM_LED PGM_LED1 PGM_LED2 D12 TEMP Description Red LED.
PAGE 28
2–20 Chapter 2: Board Components Configuration, Status, and Setup Elements Table 2–12. Board Settings DIP Switch Controls (Part 2 of 2) Switch Schematic Signal Name 3 FACTORY_LOAD 4 SECURITY_MODE Description Default ON : Load user 1 design from flash at power up. OFF OFF : Load factory design from flash at power up. ON : Do not send FACTORY command at power-up. ON OFF : Send FACTORY command at power-up.
PAGE 29
Chapter 2: Board Components Configuration, Status, and Setup Elements 2–21 PCI Express Control DIP Switch The PCI Express control DIP switch (SW6) can enable or disable different configurations. Table 2–16 shows the switch controls and descriptions. Table 2–16.
PAGE 30
2–22 Chapter 2: Board Components Configuration, Status, and Setup Elements Program Select Push Button The program select push button, PGM_SEL, is an input to the MAX V CPLD System Controller. The push button toggles the PGM_LED[2:0]setting that selects which location in the flash memory is used to configure the FPGA. Refer to Table 2–9 for the configuration settings. Table 2–20 lists the program select push button component reference and manufacturing information. Table 2–20.
PAGE 31
Chapter 2: Board Components Clock Circuitry 2–23 Clock Circuitry This section describes the board's clock inputs and outputs. On-Board Oscillators The development board includes a 50-MHz, 100-MHz, 125-MHz, and 156.25-MHz programmable oscillators. Figure 2–5 shows the default frequencies of all external clocks going to the Stratix V GX FPGA development board. Figure 2–5. Stratix V GX FPGA Development Board External Clock Inputs and Default Frequencies SMA 100 MHz CLK3 CLK2 125 MHz SDI (148.5 M / 148.
PAGE 32
2–24 Chapter 2: Board Components Clock Circuitry Table 2–22 lists the oscillators, its I/O standard, and voltages required for the development board. Table 2–22. On-Board Oscillators Source Schematic Signal Name Frequency I/O Standard Stratix V GX FPGA Device Pin Number X3 CLKIN_50 50.000 MHz 2.5V CMOS AN6 X2 CLLK_CONFIG 100.000 MHz 2.5V CMOS — X4 X1 X6 REFCLK1_QL0_P AD33 REFCLK1_QL0_N AD34 CLKINBOT_P0 AH22 CLKINBOT_N0 CLKINTOP_P0 100.
PAGE 33
Chapter 2: Board Components Clock Circuitry 2–25 Off-Board Clock Input/Output The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification. Table 2–23 lists the clock inputs for the development board. Table 2–23. Off-Board Clock Inputs I/O Standard Stratix V GX FPGA Device Pin Number CLKIN_SMA_P LVPECL — CLKIN_SMA_N LVPECL — HSMA_CLK_IN0 2.
PAGE 34
2–26 Chapter 2: Board Components General User Input/Output Memory Clocks The development board includes memory clocks which are driven to or received from the on-board memory devices. For more information on the memory clock signals, refer to the section on “Memory” on page 2–46. Table 2–25 lists the crystal oscillators component references and manufacturing information. Table 2–25. Crystal Oscillator Component References and Manufacturing Information Board Reference Description Manufacturer 148.
PAGE 35
Chapter 2: Board Components General User Input/Output 2–27 Table 2–26 lists the user-defined push button schematic signal names and their corresponding Stratix V GX FPGA device pin numbers. Table 2–26. User-Defined Push Button Schematic Signal Names and Functions Board Reference Schematic Signal Name S5 USER_PB2 S6 USER_PB1 S7 USER_PB0 I/O Standard Stratix V GX FPGA Device Pin Number Description C7 2.
PAGE 36
2–28 Chapter 2: Board Components General User Input/Output User-Defined LEDs The development board includes general and HSMC user-defined LEDs. This section describes all user-defined LEDs. For information on board specific or status LEDs, refer to“Status Elements” on page 2–18.
PAGE 37
Chapter 2: Board Components General User Input/Output 2–29 HSMC User-Defined LEDs The HSMC port A and B have two LEDs located nearby. The LEDs are labeled TX and RX. The LEDs display data flow to and from the connected HSMC cards. The LEDs are driven by the Stratix V GX FPGA device. There are no board-specific functions for the HSMC LEDs. Table 2–32 lists the HSMC user-defined LED schematic signal names and their corresponding Stratix V GX FPGA pin numbers. Table 2–32.
PAGE 38
2–30 Chapter 2: Board Components General User Input/Output Table 2–34. LCD Pin Assignments, Schematic Signal Names, and Functions Board Reference (J15) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number 10 LCD_DATA3 2.5-V AL10 LCD data bus 11 LCD_DATA4 2.5-V AP9 LCD data bus 12 LCD_DATA5 2.5-V AN9 LCD data bus 13 LCD_DATA6 2.5-V AT9 LCD data bus 14 LCD_DATA7 2.
PAGE 39
Chapter 2: Board Components Components and Interfaces 2–31 Components and Interfaces This section describes the development board's communication ports and interface cards relative to the Stratix V GX FPGA device.
PAGE 40
2–32 Chapter 2: Board Components Components and Interfaces Figure 2–6 shows the PCI Express reference clock levels. Figure 2–6. PCI Express Reference Clock Levels VMAX = 1.15 V REFCLK – VCROSS MAX = 550 mV VCROSS MIN = 250 mV REFCLK + VMIN = –0.30 V The SMB and JTAG are optional signals in the PCI Express specification. The SMB signals are wired to the Stratix V GX FPGA device and the JTAG signals control the JTAG chain if enabled by the JTAG control DIP switch (SW3.4).
PAGE 41
Chapter 2: Board Components Components and Interfaces 2–33 Table 2–37. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (J18) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description A16 PCIE_TX_P0 1.5-V PCML AU36 Transmit bus A17 PCIE_TX_N0 1.5-V PCML AU37 Transmit bus A21 PCIE_TX_P1 1.5-V PCML AR36 Transmit bus A22 PCIE_TX_N1 1.5-V PCML AR37 Transmit bus A25 PCIE_TX_P2 1.
PAGE 42
2–34 Chapter 2: Board Components Components and Interfaces 10/100/1000 Ethernet The development board supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA. The Stratix V GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function must be provided in the FPGA for typical networking applications.
PAGE 43
Chapter 2: Board Components Components and Interfaces 2–35 Table 2–39 lists the Ethernet PHY interface component reference and manufacturing information. Table 2–39. Ethernet PHY Component Reference and Manufacturing Information Board Reference U19 Description Ethernet PHY BASE-T device Manufacturer Marvel Semiconductor Manufacturing Part Number Manufacturer Website 88E1111-B2-CAAIC000 www.marvell.
PAGE 44
2–36 Chapter 2: Board Components Components and Interfaces Figure 2–8 shows the bank arrangement of signals with respect to the Samtec connector's three banks. Figure 2–8. HSMC Signal and Bank Diagram Bank 3 Power D(79.40) -orLVDS CLKIN2, CLKOUT2 Bank 2 Power D(39:0) -orD[3:0] + LVDS CLKIN1, CLKOUT1 Bank 1 8 TX Channels CDR 8 RX Channels CDR JTAG SMB CLKIN0, CLKOUT0 The HSMC interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible.
PAGE 45
Chapter 2: Board Components Components and Interfaces 2–37 Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (J1) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 26 HSMA_RX_P1 1.4-V PCML AP2 Transceiver receive channel 28 HSMA_RX_N1 1.4-V PCML AP1 Transceiver receive channel 22 HSMA_RX_P2 1.4-V PCML AM2 Transceiver receive channel 24 HSMA_RX_N2 1.
PAGE 46
2–38 Chapter 2: Board Components Components and Interfaces Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (J1) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 160 HSMA_PRSNTn 2.5-V AW8 Presence detect signal 34 HSMA_SCL 2.5-V AM29 Management serial clock line 33 HSMA_SDA 2.5-V AL29 Management serial data line 50 HSMA_RX_D_N0 LVDS or 2.5-V AW11 Data bus 56 HSMA_RX_D_N1 LVDS or 2.
PAGE 47
Chapter 2: Board Components Components and Interfaces 2–39 Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (J1) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 55 HSMA_TX_D_N1 LVDS or 2.5-V AN11 Data bus 61 HSMA_TX_D_N2 LVDS or 2.5-V AL11 Data bus 67 HSMA_TX_D_N3 LVDS or 2.5-V AF11 Data bus 73 HSMA_TX_D_N4 LVDS or 2.5-V AE11 Data bus 79 HSMA_TX_D_N5 LVDS or 2.
PAGE 48
2–40 Chapter 2: Board Components Components and Interfaces Table 2–41 lists the HSMC port B interface pin assignments, signal names, and functions. Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3) Board Reference (J2) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 30 HSMB_RX_P0 1.4-V PCML F2 Transceiver receive channel 32 HSMB_RX_N0 1.4-V PCML F1 Transceiver receive channel 26 HSMB_RX_P1 1.
PAGE 49
Chapter 2: Board Components Components and Interfaces 2–41 Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference (J2) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 110 HSMB_A12 2.5-V CMOS D18 Memory address bit 114 HSMB_A13 2.5-V CMOS A19 Memory address bit 116 HSMB_A14 2.5-V CMOS B19 Memory address bit 128 HSMB_A15 2.5-V CMOS C19 Memory address bit 43 HSMB_ADDR_CMD0 2.
PAGE 50
2–42 Chapter 2: Board Components Components and Interfaces Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference (J2) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 107 HSMB_DQ18 2.5-V CMOS N14 Memory data bus 109 HSMB_DQ19 2.5-V CMOS M14 Memory data bus 113 HSMB_DQ20 2.5-V CMOS U14 Memory data bus 115 HSMB_DQ21 2.5-V CMOS L15 Memory data bus 119 HSMB_DQ22 2.
PAGE 51
Chapter 2: Board Components Components and Interfaces 2–43 Table 2–42 lists the HSMC connector component reference and manufacturing information. Table 2–42. HSMC Connector Component Reference and Manufacturing Information Board Reference J1 and J2 Description HSMC, custom version of QSH-DP family high-speed socket. Manufacturer Manufacturing Part Number Manufacturer Website Samtec ASP-122953-01 www.samtec.
PAGE 52
2–44 Chapter 2: Board Components Components and Interfaces Table 2–45 shows the cable equalizer lengths. Table 2–45. SDI Cable Equalizer Lengths Data Rate (Mbps) Cable Type Maximum Cable Length (m) 270 400 1485 Belden 1694A 140 2970 120 Figure 2–9 is an excerpt from the LMH0384 cable equalizer data sheet which shows the SDI cable equalizer. Figure 2–9. SDI Cable Equalizer SDI Adaptive Cable Equalizer 1.0 μF 75 Ω Coaxial Cable SDI SDO To FPGA 1.0 μF SDO SDI 3.
PAGE 53
Chapter 2: Board Components Components and Interfaces 2–45 Table 2–47 lists the SDI connector component reference and manufacturing information. Table 2–47. HSMC Connector Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U25 3-Gbps HD/SD SDI cable driver National Semiconductor LMH0303SQ www.national.com U24 3-Gbps HD/SD SDI adaptive cable equalizer National Semiconductor LMH0384SQ www.national.
PAGE 54
2–46 Chapter 2: Board Components Memory Table 2–48. 40G QSFP Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (J12) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description 11 QSFP_SCL 3.3-V LVTTL AD30 QSFP serial 2-wire clock 12 QSFP_SDA 3.3-V LVTTL AC30 QSFP serial 2-wire data Table 2–49 lists the QSFP interface component reference and manufacturing information. Table 2–49.
PAGE 55
Chapter 2: Board Components Memory 2–47 Table 2–50 lists the DDR3 devices pin assignments, signal names, and functions. Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4) Board Reference (U12, U17, U21, U23, U28) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description DDR3 x16 / DDR3 x8 pins T3 DDR3_A13 1.5-V SSTL Class I J31 Address bus N7 DDR3_A12 1.5-V SSTL Class I R30 Address bus R7 DDR3_A11 1.
PAGE 56
2–48 Chapter 2: Board Components Memory Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (U12, U17, U21, U23, U28) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description U28.H7 DDR3_DQ7 1.5-V SSTL Class I G28 Data bus byte lane 0 U28.E7 DDR3_DM0 1.5-V SSTL Class I A29 Write mask byte lane 0 U28.F3 DDR3_DQS_P0 1.5-V SSTL Class I H29 Data strobe P byte lane 0 U28.G3 DDR3_DQS_N0 1.
PAGE 57
Chapter 2: Board Components Memory 2–49 Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (U12, U17, U21, U23, U28) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description U21.F7 DDR3_DQ33 1.5-V SSTL Class I F24 Data bus byte lane 4 U21.F2 DDR3_DQ34 1.5-V SSTL Class I C25 Data bus byte lane 4 U21.F8 DDR3_DQ35 1.5-V SSTL Class I G24 Data bus byte lane 4 U21.H3 DDR3_DQ36 1.
PAGE 58
2–50 Chapter 2: Board Components Memory Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (U12, U17, U21, U23, U28) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description U17.B8 DDR3_DQ62 1.5-V SSTL Class I G20 Data bus byte lane 7 U17.A3 DDR3_DQ63 1.5-V SSTL Class I E20 Data bus byte lane 7 U17.D3 DDR3_DM7 1.5-V SSTL Class I B20 Write mask byte lane 7 U17.C7 DDR3_DQS_P7 1.
PAGE 59
Chapter 2: Board Components Memory 2–51 Table 2–52 lists the QDRII+ pin assignments, signal names, and functions. Table 2–52. QDRII+ Pin Assignments, Signal Names and Functions (Part 1 of 2) Board Reference (U5) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description A2 QDRII_A20 1.8-V HSTL Class I AA13 Address bus (reserved for 144M) A10 QDRII_A19 1.8-V HSTL Class I AP12 Address bus (reserved for 72M) A3 QDRII_A18 1.
PAGE 60
2–52 Chapter 2: Board Components Memory Table 2–52. QDRII+ Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U5) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description N11 QDRII_D1 1.8-V HSTL Class I AB16 Write data bus P10 QDRII_D0 1.8-V HSTL Class I AD15 Write data bus B6 QDRII_K_P 1.8-V HSTL Class I AK14 Write clock P A6 QDRII_K_N 1.8-V HSTL Class I AL14 Write clock N A4 QDRII_WPSn 1.
PAGE 61
Chapter 2: Board Components Memory 2–53 RLDRAM II The development board supports a 32Mx18x8 bank CIO RLDRAM II SRAM interface for very-high-speed sequential memory access. The 18-bit data bus comprises of a single x18 device with a single address or command bus. This interface connects to the vertical I/O banks on the bottom edge of the FPGA. The target speed is 533 MHz. Table 2–54 lists the RLDRAM II pin assignments, signal names, and functions. Table 2–54.
PAGE 62
2–54 Chapter 2: Board Components Memory Table 2–54. RLDRAM II Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U20) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description B10 RLDC_DQ0 1.8-V HSTL Class I AW26 Write data C10 RLDC_DQ1 1.8-V HSTL Class I AN27 Write data E10 RLDC_DQ2 1.8-V HSTL Class I AN26 Write data F10 RLDC_DQ3 1.8-V HSTL Class I AM26 Write data B3 RLDC_DQ4 1.8-V HSTL Class I AV26 Write data C3 RLDC_DQ5 1.
PAGE 63
Chapter 2: Board Components Memory 2–55 Flash The development board has two 512-Mb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, test application data, and user code space. Each interface has a 16-bit data bus and the two devices combined allow for x32 FPP configuration. This device is part of the shared flash and MAX (FM) bus, which connects to the flash memory and MAX V CPLD System Controller.
PAGE 64
2–56 Chapter 2: Board Components Memory Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference (U10, U11) Schematic Signal Name I/O Standard Stratix V GX FPGA Device Pin Number Description U11.E7 FM_D31 1.8-V AT24 Data bus U11.G7 FM_D30 1.8-V AV25 Data bus U11.H5 FM_D29 1.8-V AW25 Data bus U11.F5 FM_D28 1.8-V AL25 Data bus U11.F4 FM_D27 1.8-V AL24 Data bus U11.F3 FM_D26 1.8-V AJ24 Data bus U11.E3 FM_D25 1.
PAGE 65
Chapter 2: Board Components Power Supply 2–57 Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference (U10, U11) I/O Standard Stratix V GX FPGA Device Pin Number FLASH_RDYBSYn1 1.8-V AN7 Ready D4 FLASH_RESETn 1.8-V AJ6 Reset G8 FLASH_WEn 1.8-V AN8 Write enable C6 FLASH_WPn — — Write protect U11.F7 Schematic Signal Name Description Table 2–57 lists the flash memory component reference and manufacturing information. Table 2–57.
PAGE 66
2–58 Chapter 2: Board Components Power Supply Figure 2–10 shows the power distribution system on the development board. Figure 2–10. Power Distribution System Power Sequencing: 1 2 3 4 5 6 VCC/VCCHIP/VCCHSSI VCCPD/VCCPGM/VCCAUX/VCCA_FPLL VCCIO VCCR_GXB/VCCT_GXB VCCA_GXB VCCPT/VCCH_GXB/VCCD_FPLL 12V 1.675A 1.741A 5.0V 1.080A 1.226A LTM4614 Dual 4A Switching Regulator (+/- 2%) RSENSE 1.0V 2.395A 1.2V, 2.395A 1.5V 1.499A 1.6V, 1.499A RSENSE 5.0V LTM4628 Dual 8A Switching Regulator (+/- 3%) 5.0V 0.
PAGE 67
Chapter 2: Board Components Power Supply 2–59 Power Measurement There are 16 power supply rails which have on-board voltage, current, and wattage sense capabilities. These 8-channel differential 24-bit ADC devices and rails are split from the primary supply plane by a low-value sense resistor for the ADC to measure voltage and current. A serial peripheral interface (SPI) bus connects these ADC devices to the MAX V CPLD System Controller as well as the Stratix V GX FPGA.
PAGE 68
2–60 Chapter 2: Board Components Temperature Sense Table 2–59. Power Rail Measurements Based on the GUI Selection (Part 2 of 2) Number 5 6 Schematic Signal Name Voltage (V) 1.5 S5_VCC_1p5 2.5 S5_VCCIO_2.5V 7 S5_VCCIO_1.5V 1.5 8 S5_VCCA_GXB 3.
PAGE 69
Chapter 2: Board Components Statement of China-RoHS Compliance 2–61 Table 2–61 lists the temperature sense interface pin assignments, signal names, and functions. Table 2–61.
PAGE 70
2–62 Stratix V GX FPGA Development Board Reference Manual Chapter 2: Board Components Statement of China-RoHS Compliance October 2014 Altera Corporation
PAGE 71
A. Board Revision History This appendix catalogs revisions to the Stratix V GX FPGA development board. Table A–1 lists the versions of all releases of the Stratix V GX FPGA development board. Table A–1. Stratix V GX FPGA Development Board Revision History Version Production silicon Engineering silicon (ES) October 2014 Altera Corporation Release Date July 2012 August 2011 Description Production device. Initial release.
PAGE 72
A–2 Stratix V GX FPGA Development Board Reference Manual Appendix A: Board Revision History October 2014 Altera Corporation
PAGE 73
Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table shows the revision history for this document. Date Version October 2014 April 2014 July 2012 1.5 1.4 Changes ■ Fixed typos in the Flash Pin Assignments, Schematic Signal Names, and Functions table in Chapter 2. ■ Changed the standard I/O for the transmit bus (PCI Express Pin Assignments, Schematic Signal Names, and Functions) to 1.5-V PCML from 1.4-V.
PAGE 74
Info–2 Additional InformationAdditional Information Document Revision History Date October 2011 Version Changes ■ Updated the transceiver speed to 12.5 Gbps. ■ Revised the FPGA device pin numbers that connect to the on-board oscillator signals: ■ CLKINBOT_N0: Changed from AW29 to AJ22 ■ CLK_125_P: Changed from AH22 to AV29 ■ CLK_125_N: Changed from AJ22 to AW29 Revised the FPGA device pin number that connects to the PCI Express SMB clock signal, PCIE_SMBCLK—changed from AP34 to AN33.
PAGE 75
Additional InformationAdditional Information How to Contact Altera Info–3 How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact (1) Technical support Technical training Product literature Contact Method Address Website www.altera.com/support Website www.altera.com/training Email custrain@altera.com Website www.altera.com/literature Nontechnical support (general) Email nacomp@altera.
PAGE 76
Info–4 Additional InformationAdditional Information Typographic Conventions Visual Cue Meaning h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.