Stratix V GX FPGA Development Kit User Guide Stratix V GX FPGA Development Kit User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01103-1.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
Contents Chapter 1. About This Kit Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv Contents Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 Start . . . . . . .
Contents v Set New Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Configuring the FPGA Using the Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Before Configuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Configuring the FPGA . . . . . . . . . . . . . . . . . . . .
vi Stratix V GX FPGA Development Kit User Guide Contents December 2014 Altera Corporation
1. About This Kit The Altera® Stratix® V GX FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix V GX FPGA designs. The following list describes what you can accomplish with the kit: ■ Test signal quality of the FPGA transceiver I/Os (10 Gbps+). ■ Develop and test PCI Express® (PCIe) 3.0 designs. ■ Develop and test memory subsystems consisting of SyncFlash, DDR3, and QDRII+.
1–2 Chapter 1: About This Kit Kit Features ■ Power supply and cables—The kit includes the following items: ■ Power supply and AC adapters for North America/Japan, Europe, and the United Kingdom ■ Standard USB A to micro-USB cable ■ Ethernet cable ■ 75 SMB video cable Software The software for this kit, described in the following sections, is available on the Altera website for immediate downloading. You can also request to have Altera mail the software to you on DVDs.
Chapter 1: About This Kit Kit Features 1–3 ■ Nios® II Embedded Design Suite (EDS)—A full-featured set of tools that allows you to develop embedded software for the Nios II processor that you can include in your Altera FPGA designs. Stratix V GX FPGA Development Kit Installer The license-free Stratix V GX FPGA Development Kit installer includes all the documentation and design examples for the kit. For information on installing the Development Kit Installer, refer to “Software Installation” on page 3–1.
1–4 Stratix V GX FPGA Development Kit User Guide Chapter 1: About This Kit Kit Features December 2014 Altera Corporation
2.
2–2 Chapter 2: Getting Started References References Use the following links to check the Altera website for other related information: ■ For the latest board design files and reference designs, refer to the Stratix V GX FPGA Development Kit page. ■ For additional daughter cards available for purchase, refer to the Development Board Daughtercards page. ■ For the Stratix V GX device documentation, refer to the Literature: Stratix V Devices page.
3. Software Installation This chapter explains how to install the following software: ■ Quartus II Subscription Edition Software ■ Stratix V GX FPGA Development Kit ■ USB-Blaster™ II driver Installing the Quartus II Subscription Edition Software Included in the Quartus II Subscription Edition Software are the Quartus II software (including Qsys), the Nios II EDS, and the MegaCore IP Library. To install the Altera development tools, perform the following steps: 1.
3–2 Chapter 3: Software Installation Installing the Stratix V GX FPGA Development Kit 5. In the Find/Activate Products dialog box, enter your development kit serial number and click Search. 6. When your product appears, turn on the check box next to the product name. 7. Click Activate Selected Products, and click Close. 8. When licensing is complete, Altera emails a license.dat file to you.
Chapter 3: Software Installation Installing the USB-Blaster II Driver 3–3 The installation program creates the Stratix V GX FPGA Development Kit directory structure shown in Figure 3–1. Figure 3–1. Stratix V GX FPGA Development Kit Installed Directory Structure (1) The default Windows installation directory is C:\altera\\.
3–4 Stratix V GX FPGA Development Kit User Guide Chapter 3: Software Installation Installing the USB-Blaster II Driver December 2014 Altera Corporation
4. Development Board Setup Setting Up the Board To prepare and apply power to the board, perform the following steps: 1. The Stratix V GX FPGA development board ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be currently configured with the default settings, follow the instructions in “Factory Default Switch Settings” on page 4–1 to return the board to its factory settings before proceeding. 2.
4–2 Chapter 4: Development Board Setup Factory Default Switch Settings Figure 4–1 shows the switch locations and the default position of each switch on the top side of the board. Figure 4–1. Switch Locations and Default Settings on the Board Top SW1 8 7 6 5 4 3 2 1 OFF = 1 ON ON = 0 User DIP Switch Default: no jumper installed for 2.5-V VCCIO J8 1.8 V 1.5 V 1.
Chapter 4: Development Board Setup Factory Default Switch Settings 4–3 Figure 4–2 shows the switch locations and the default position of each switch on the bottom side of the board. MAXV HSMA HSMB PCIE Figure 4–2.
4–4 Chapter 4: Development Board Setup Factory Default Switch Settings 2. Set the DIP switch bank (SW3) to match Table 4–2 and Figure 4–2. (1) Table 4–2. SW3 JTAG DIP Switch Settings Switc h Board Label Default Position Function Switch 1 has the following options: ■ 1 MAX_JTAG_EN ■ When on (0), removes the MAX V system controller in the JTAG chain. Off When off (1), includes the MAX V system controller from the JTAG chain.
Chapter 4: Development Board Setup Factory Default Switch Settings 4–5 4. Set DIP switch bank (SW5) to match Table 4–4 and Figure 4–2. 1 If you use an external USB Blaster, Altera recommends that you disable the power-up configuration of the FPGA by changing the MSEL(4:0) DIP switch (SW4) from 01000 to 11000. This will prevent power-up FPGA configuration from flash in the default FPPx32 mode.
4–6 Chapter 4: Development Board Setup Factory Default Switch Settings 5. Set DIP switch bank (SW6) to match Table 4–5 and Figure 4–2. Table 4–5. SW6 DIP Switch Settings Switc h Board Label Default Position Function Switch 1 has the following options: 1 PCIE_PRSNT2 n_x1 ■ When on (0), x1 presence detect is enabled. ■ When off (1), x1 presence detect is disabled. On Switch 2 has the following options: 2 PCIE_PRSNT2 n_x4 ■ When on (0), x4 presence detect is enabled.
5. Board Update Portal The Stratix V GX FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board. The design consists of a Nios II embedded processor, an Ethernet MAC, and an HTML web server. When you power up the board with the DIP switch SW5.3 in the off position, the Stratix V GX FPGA configures with the Board Update Portal design example.
5–2 Chapter 5: Board Update Portal Using the Board Update Portal to Update User Designs f You can also navigate directly to the Stratix V GX FPGA Development Kit page of the Altera website to determine if you have the latest kit software. Using the Board Update Portal to Update User Designs The Board Update Portal allows you to write new designs to the user hardware 1 portion of flash memory. Designs must be in the Nios II Flash Programmer File (.flash) format.
6. Board Test System The kit includes design examples and an application called the Board Test System to test the functionality of the Stratix V GX FPGA development board. The application provides an easy-to-use interface to alter functional settings and observe the results. You can use the application to test board components, modify functional parameters, observe performance, and measure power usage.
6–2 Chapter 6: Board Test System Preparing the Board After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components. The Power Monitor button starts the Power Monitor application that measures and reports current power and temperature information for the board.
Chapter 6: Board Test System Using the Board Test System 1 6–3 If you power up your board with the DIP switch SW5.3 in a position other than the on (user hardware 1) position, or if you load your own design into the FPGA with the Quartus II Programmer, you receive a message prompting you to configure your board with a valid Board Test System design. Refer to “The Configure Menu” for information about configuring your board.
6–4 Chapter 6: Board Test System Using the Board Test System Board Information The Board information control displays static information about your board. ■ Board Name—Indicates the official name of the board. ■ Board P/N—Indicates the part number of the board. ■ Serial number—Indicates the serial number of the board. ■ Factory test version—Indicates the version of the Board Test System currently running on the board. ■ MAX V ver—Indicates the version of MAX V code currently running on the board.
Chapter 6: Board Test System Using the Board Test System ■ 1 6–5 PSO—Sets the MAX V PSO register. The following options are available: ■ Use PSR—Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration. ■ Use PSS—Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration. ■ PSS—Displays the MAX V PSS register value. Refer to Table 6–1 for the list of available options. ■ PSR—Sets the MAX V PSR register.
6–6 Chapter 6: Board Test System Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I/O components on your board. You can write to the character LCD, read DIP switch settings, turn LEDs on or off, and detect push button presses. Figure 6–3 shows the GPIO tab. Figure 6–3. The GPIO Tab The following sections describe the controls on the GPIO tab.
Chapter 6: Board Test System Using the Board Test System 6–7 User LEDs The User LEDs control displays the current state of the user LEDs. To toggle the board LEDs, click the 0 to 7 buttons to toggle red or green LEDs, the All button, and the graphical representation of the LEDs. Push Button Switches The read-only Push button switches control displays the current state of the board user push buttons. Press a push button on the board to see the graphical display change accordingly.
6–8 Chapter 6: Board Test System Using the Board Test System Read The Read control reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table. The flash memory addresses display in the format the Nios II processor within the FPGA uses, that is, each flash memory address is offset by 0x0800.0000. Thus, the first location in flash memory appears as 0x0800.0000 in the GUI.
Chapter 6: Board Test System Using the Board Test System 6–9 The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board. Figure 6–5 shows the DDR3 tab. Figure 6–5. The DDR3 Tab The following sections describe the controls on the DDR3 tab. Start The Start control initiates DDR3 memory transaction performance analysis. Stop The Stop control terminates transaction performance analysis.
6–10 Chapter 6: Board Test System Using the Board Test System ■ Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of data analyzed per second. The data bus is 72 bits wide and the frequency is 533MHz double data rate (1066Mbps per pin), equating to a theoretical maximum bandwidth of 9594MBps. Error Control Displays data errors detected during analysis and allows you to insert errors: ■ Detected errors—Displays the number of data errors detected in the hardware.
Chapter 6: Board Test System Using the Board Test System 6–11 The QDRII+ Tab The QDRII+ tab allows you to read and write the QDR II+ memory on your board and independently test each QDR II+ port. Figure 6–6 shows the QDRII+ tab. Figure 6–6. The QDRII+ Tab The following sections describe the controls on the QDRII+ tab. Start The Start control initiates QDR II+ memory transaction performance analysis. Stop The Stop control terminates transaction performance analysis.
6–12 Chapter 6: Board Test System Using the Board Test System Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: ■ Write and Read performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve. ■ Write (MBps) and Read (MBps)—Show the number of bytes of data analyzed per second.
Chapter 6: Board Test System Using the Board Test System 6–13 The XCVR1 Tab The XCVR1 tab allows you to perform loopback tests on the SDI and HSMA Transceivers, HSMA LVDS, and HSMA CMOS Parallel interfaces. Figure 6–7 shows the XCVR1 tab. Figure 6–7. The XCVR1 Tab 1 You must have the loopback HSMC installed on the HSMC connector Port A and the SDI loopback cable for all tests to function in external loopback mode. Otherwise, set the PMA setting tab to test internal loopback mode (serial loopback = 1).
6–14 Chapter 6: Board Test System Using the Board Test System ■ Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected after channel lock is acquired. Port The Port control allows you to specify which interface to test. The following port tests are available: ■ SDI (2.97 Gbps) ■ HSMA Transceivers x8 (10 Gbps+) ■ HSMA x3 CMOS (50 Mbps) ■ HSMA x17 LVDS (1.
Chapter 6: Board Test System Using the Board Test System 6–15 ■ HF2—Selects second lowest frequency divide-by-22 data pattern ■ LF—Selects lowest frequency divide by 33 data pattern Error Control Displays data errors detected during analysis and allows you to insert errors: ■ Detected errors—Displays the number of data errors detected in the hardware. ■ Inserted errors—Displays the number of errors inserted into the transmit data stream.
6–16 Chapter 6: Board Test System Using the Board Test System The XCVR2 Tab The XCVR2 tab allows you to perform loopback tests on the QSFP and HSMB Transceivers, and HSMB Parallel interfaces. Figure 6–8 shows the XCVR2 tab. Figure 6–8. The XCVR2 Tab 1 You must have the loopback HSMC installed on the HSMC port B connector this test to work correctly. Unless you have a QSFP loopback module, you will need test the QSFP in the internal loopback mode (serial loopback = 1).
Chapter 6: Board Test System Using the Board Test System ■ 6–17 Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected after channel lock is acquired. Port The Port control allows you to specify which interface to test.
6–18 Chapter 6: Board Test System Using the Board Test System ■ LF—Selects lowest frequency divide by 33 data pattern Error Control This control displays data errors detected during analysis and allows you to insert errors: ■ Detected errors—Displays the number of data errors detected in the hardware. ■ Inserted errors—Displays the number of errors inserted into the transmit data stream. ■ Insert Error—Inserts a one-word error into the transmit data stream each time you click the button.
Chapter 6: Board Test System Using the Board Test System 6–19 The XCVR3 Tab The XCVR3 tab allows you to perform loopback tests on the SMA port. Figure 6–9 shows the XCVR3 tab. Figure 6–9. The XCVR3 Tab 1 The external loopback mode will not pass due to only having a transmit port available. To test in internal loopback, adjust the setting using the PMA button (serial loopback = 1). The following sections describe the controls on the XCVR3 tab.
6–20 Chapter 6: Board Test System Using the Board Test System ■ Pattern sync—Shows the pattern synced or not synced state when the internal loopback is enabled. The pattern is considered synced when the start of the data sequence is detected after channel lock is acquired. Port The Port control allows you to specify which interface to test.
Chapter 6: Board Test System The Power Monitor 6–21 ■ HF2—Selects second lowest frequency divide-by-22 data pattern ■ LF—Selects lowest frequency divide by 33 data pattern Error Control This control displays data errors detected during analysis and allows you to insert errors: ■ Detected errors—Displays the number of data errors detected in the hardware. ■ Inserted errors—Displays the number of errors inserted into the transmit data stream.
6–22 Chapter 6: Board Test System The Power Monitor The Power Monitor communicates with the MAX V device on the board through the JTAG bus. A power monitor circuit attached to the MAX V device allows you to measure the power that the Stratix V GX FPGA device is consuming regardless of the design currently running. Figure 6–10 shows the Power Monitor. Figure 6–10. The Power Monitor The following sections describe the Power Monitor controls.
Chapter 6: Board Test System The Clock Control 6–23 f A table with the power rail information is available in the Stratix V GX FPGA Development Board Reference Manual. Temperature Information The Temperature information controls display the following temperature readings for the board and the FPGA on the board: ■ FPGA—Indicates the temperature of the FPGA device. ■ Board—Indicates the overall board temperature.
6–24 Chapter 6: Board Test System The Clock Control The Clock Control application runs as a stand-alone application. ClockControl.exe resides in the \kits\stratixVGX_5sgxea7kf40_fpga\examples\board_test_system directory. On Windows, click Start > All Programs > Altera > Stratix V GX FPGA Development Kit > Clock Control to start the application.
Chapter 6: Board Test System Configuring the FPGA Using the Quartus II Programmer 6–25 Default The Default control sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board. Set New Frequency The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the Si570/Si571 and the Frequency controls for the Si5338 (U38 and U46).
6–26 Stratix V GX FPGA Development Kit User Guide Chapter 6: Board Test System Configuring the FPGA Using the Quartus II Programmer December 2014 Altera Corporation
A. Programming the Flash Memory Device CFI Flash Memory Map Table A–1 shows the default memory contents of two interlaced 512-Mbyte CFI flash devices. Each flash device has a 16-bit data bus and the two combined flash devices allow for a 32-bit flash memory interface. For the Board Update Portal to run correctly and update designs in the user memory, this memory map must not be altered. Table A–1.
A–2 Appendix A: Programming the Flash Memory Device Programming Flash Memory Using the Board Update Portal The Nios II EDS sof2flash command line utility converts your Quartus II-compiled .sof into the .flash format necessary for the flash device. Similarly, the Nios II EDS elf2flash command line utility converts your compiled and linked .elf software design to .flash.
Appendix A: Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings A–3 1. Set the DIP switch SW5.3 to the off position (factory design) to load the Board Update Portal design from flash memory on power up. 2. Attach the USB cable and power up the board. 3. If the board has powered up and the LCD displays either Connecting... or a valid IP address (such as 152.198.231.75), proceed to step 8.
A–4 Appendix A: Programming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings 3. Click Add File and select \kits\stratixVGX_5sgxea7kf40_fpga\factory_recovery\s5gxea7_fpga_bup.s of. 4. Turn on the Program/Configure option for the added file. 5. Click Start to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100%. The Config Done LED (D17) illuminates indicating that the flash device is ready for programming. 6.
Appendix A: Programming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings 1 A–5 DIP switch SW3.1 set to on includes the MAX V device in the JTAG chain. 2. Launch the Quartus II Programmer. 3. Click Auto Detect. 4. Click Add File and select \kits\stratixVGX_5sgxea7kf40_fpga\factory_recovery\max5.pof. 5. Turn on the Program/Configure option for the added file. 6. Click Start to download the selected configuration file to the MAX V CPLD.
A–6 Stratix V GX FPGA Development Kit User Guide Appendix A: Programming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings December 2014 Altera Corporation
Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table shows the revision history for this document. Date Version Changes December 2014 1.4 Switch location figure now shows the correct VCCIO values for J8. February 2014 1.3 Update to correct sof2flash and elf2flash commands. July 2012 1.2 Updates supporting the Quartus II software version 12.0 release. March 2012 1.
Info–2 Additional Information Typographic Conventions Visual Cue Meaning Indicates variables. For example, n + 1. italic type Variable names are enclosed in angle brackets (< >). For example, and .pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. “Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.
