Stratix II Professional Filtering Lab Application Note 393 August 2005, version 1.0 Introduction The Stratix ® II filtering lab design in the DSP Development Kit, Stratix II Professional Edition, shows you how to use the Altera® DSP Builder for system design, simulation, and board-level verification. The DSP Builder digital signal processing (DSP) development tool interfaces The MathWorks industry’s leading model-based design tool, Simulink, with the Altera Quartus® II development software.
Stratix II Professional Filtering Lab Installing the Stratix II Professional Filtering Lab Files These instructions in this application note assume that you have already installed the software provided with the DSP Development Kit, Stratix II Professional Edition on your PC. f For installation instructions, see the DSP Development Kit, Stratix II Professional Edition Getting Started User Guide.
Stratix II Professional Filtering Lab Before You Begin You must have the following software installed on your PC: ■ ■ ■ ■ ■ ■ 1 Quartus II software version 5.0 Service Pack 1 DSP Builder version 5.0.1 FIR Compiler MegaCore function version 3.2.1 NCO Compiler MegaCore function version 2.2.2 The MathWorks Release 14 with Service Pack 2 (R14SP2): ● MATLAB version 7.0.4 ● Simulink version 6.2 (Optional) ModelSim-Altera, ModelSim PE, or ModelSim SE version 6.
Stratix II Professional Filtering Lab Figure 2. Setting the MATLAB Current Directory to DSPBuilder\AltLib and Running the Setup Script 4. Exercise 1: Review the Filtering Lab Design When you see “DSP Builder v5.0.1 setup completed,” as shown in Figure 2, this procedure is complete. You can now use the exercises in the filtering lab design. To review the filtering lab design, follow these steps: 1. Run the MATLAB software. 2.
Stratix II Professional Filtering Lab 4. Review the Simulink design (see Figure 4). The filtering lab design contains a combination of OpenCore® Plus DSP MegaCore functions and DSP Builder blocks. The OpenCore Plus feature lets you test-drive Altera MegaCore functions for free. You can verify the functionality of a MegaCore function quickly and easily, as well as evaluate its size and speed before purchasing the software.
Stratix II Professional Filtering Lab Figure 4 shows the top-level schematic for the filtering lab design. Two numerically controlled oscillators (NCOs) generate a 1-MHz sinusoidal signal and a 10-MHz sinusoidal signal respectively. The signals are added together and then passed to a low-pass filter with a cut-off frequency of 3 MHz. The low-pass filter removes the 10-MHz sinusoidal signal and allows the 1-MHz sinusoidal signal through to the fir_result output. Figure 4.
Stratix II Professional Filtering Lab Review the NCO_1MHz MegaCore Function Instance To review the parameters for the NCO_1MHz MegaCore function, follow these steps: 1. Double-click the NCO_1MHz block (see Figure 4) to launch IP Toolbench for the NCO Compiler MegaCore function, as shown in Figure 5. Figure 5. IP Toolbench for NCO Compiler MegaCore Function v2.2.2 2. 7 Click Step 1: Parameterize to review the parameters for the NCO_1MHz block (see Figure 6 and Figure 7 on page 10).
Stratix II Professional Filtering Lab a. Review the parameters in the Parameters tab. The parameters should be set as shown in Figure 6, and are listed in Table 1. Figure 6.
Stratix II Professional Filtering Lab Table 1 lists the parameters for the NCO_1MHZ block that you can set in the Parameters tab. Table 1.
Stratix II Professional Filtering Lab b. Review the parameters in the Implementation tab. The parameters should be set as shown in Figure 7, and are listed in Table 2. Figure 7.
Exercise 1: Review the Filtering Lab Design Table 2 lists the parameters for the NCO_1MHz block that you can set in the Implementation tab. Table 2. NCO_1MHz Compiler - Implementation Tab Parameter Value Under Device Family Target Stratix II Under Outputs Single Output Select Under Multi-Channel NCO Number of Channels 1 Under Multiplier-Based Architecture Use Dedicated Multiplier(s) Clock Cycles Per Output Altera Corporation Select 1 3.
Stratix II Professional Filtering Lab Review the NCO_10MHz MegaCore Function Instance To review the parameters for the NCO_10MHz MegaCore function, follow these steps: 1. Double-click the NCO_10MHz block (see Figure 4 on page 6) to launch IP Toolbench for the NCO Compiler MegaCore function, see Figure 5 on page 7. 2. Under Hardware Compilation, under Single step compilation, click Step 1: Parameterize to review the parameters for the NCO_10MHz block (see Figure 8 and Figure 9 on page 14).
Exercise 1: Review the Filtering Lab Design Table 3 lists the parameters for the NCO_10MHz block that you can set in the Parameters tab. Table 3.
Stratix II Professional Filtering Lab b. Review the parameters in the Implementation tab. The parameters should be set as shown in Figure 9, and are listed in Table 4. Figure 9.
Exercise 1: Review the Filtering Lab Design Table 4 lists the parameters for the NCO_10MHz block that you can set in the Implementation tab. Table 4. NCO_10MHz Compiler - Implementation Tab Parameter Value Under Device Family Target Stratix II Professional Under Outputs Single Output Select Under Multi-Channel NCO Number of Channels 1 Under Multiplier-Based Architecture Use Dedicated Multiplier(s) Clock Cycles Per Output Altera Corporation Select 1 3.
Stratix II Professional Filtering Lab Review the FIR_3MHz MegaCore Function Instance To review the parameters for the FIR_3MHz MegaCore function, follow these steps: 1. Double-click the FIR_3MHz block (see Figure 4 on page 6) to launch IP Toolbench for the FIR Compiler MegaCore function, as shown in Figure 10. Figure 10. IP Toolbench for FIR Compiler MegaCore Function v3.2.1 2. Click Step 1: Parameterize to review the parameters for the FIR_3MHz block (see Figure 12 on page 19).
Exercise 1: Review the Filtering Lab Design a. Review the parameters in the Coefficients Generator Dialog dialog box. The parameters should be set as shown in Figure 11, and are listed in Table 5. Figure 11.
Stratix II Professional Filtering Lab Table 5 lists the parameters for the FIR_3MHz block in the Coefficients Generator Dialog dialog box. Table 5. Parameters in the Coefficients Generator Dialog Box Parameter Value Under Coefficients Name Low Pass Set Under Floating Coefficients Set Rate Specification Single Rate Filter Type Low Pass Window Type Blackman Coefficients 35 Cutoff Freq. 1 3.0E6 Hz Sample Rate 1.0E8 Hz b.
Exercise 1: Review the Filtering Lab Design c. Review the architecture and implementation options for the FIR_3MHz block in the Parameterize - FIR Compiler MegaCore Function dialog box. The parameters should be set as shown in Figure 12, and are listed in Table 6. Figure 12.
Stratix II Professional Filtering Lab Table 6 lists the parameters for the FIR_3MHz block in the Parameterize - FIR Compiler MegaCore Function dialog box. Table 6.
Exercise 2: Simulate the Model in Simulink Exercise 2: Simulate the Model in Simulink To simulate the model in the Simulink software, follow these steps: 1. Choose Configuration Parameters (Simulation menu, see Figure 4 on page 6). The settings for the Simulink simulation parameters should be the same as those shown in Figure 13. Figure 13. Configuration Parameters: filter_design/Configuration Dialog Box Altera Corporation 2. Click OK. 3. Start the simulation by choosing Start (Simulation menu).
Stratix II Professional Filtering Lab 5. Click the binocular icon to auto-scale the waveforms. Figure 14 shows the scaled waveforms in the time domain for the unfiltered data. Figure 14. Time Domain Plot of adder_result_sim—Unfiltered Data Figure 15 shows the scaled waveforms in the time domain for the filtered data. Figure 15. Time Domain Plot of fir_result_sim—Filtered Data 6. Switch to the MATLAB Command Window. 7.
Exercise 2: Simulate the Model in Simulink Parameters in this command line include the following: • • • adder_result_sim is the name of the signal at the output of the adder. Frequency Response – Unfiltered Data is the title of the plot. 10e7 is the sampling frequency (100 MHz), which is well above the Nyquist frequency. A MATLAB plot displays the frequency response of the unfiltered data, as shown in Figure 16. Figure 16. FFT Response of adder_result_sim - Unfiltered Data b.
Stratix II Professional Filtering Lab Parameters in this command line include the following: • • • fir_result_sim is the name of the signal at the output of the FIR filter. Frequency Response – Filtered Data is the title of the plot. 10e7 is the sampling frequency (100 MHz), which is well above the Nyquist frequency. A MATLAB plot displays the frequency response of the filtered data, as shown in Figure 17. Figure 17.
Exercise 3: Perform RTL Simulation (Optional) Exercise 3: Perform RTL Simulation (Optional) Exercise 3 performs RTL simulation using the ModelSim simulation tool. Generate Simulation Files (Optional) To generate the simulation files for the filtering lab design example, follow these steps: 1. Double-click the SignalCompiler block (see Figure 4 on page 6) to display the SignalCompiler dialog box, as shown in Figure 18. Figure 18. SignalCompiler 5.0.1- page 1 of 2, Analyze Feature Altera Corporation 2.
Stratix II Professional Filtering Lab Figure 19. Signal Compiler 5.0.1 - page 2 of 2, Hardware Compilation Feature 26 4. Under Project Settings Options, in the Synthesis tool list, select Quartus II. 5. Under Project Settings Options, click the Testbench tab and turn on Generate Stimuli for VHDL Testbench. 6. Under Hardware Compilation, under Single step compilation, click 1 - Convert MDL to VHDL. The SignalCompiler generates a simulation script, tb_filter_design.
Stratix II Professional Filtering Lab Perform RTL Simulation in ModelSim (Optional) To perform RTL simulation with the ModelSim software, follow these steps: 1. Run the ModelSim software. 2. Choose Change Directory (File menu) and browse to the directory: \StratixII_Pro_DSP_Kit-v1.0.0\Examples\HW\ Lab\Filtering\Exercises1and2and3 3. Click OK. 4. Choose Execute Macro (Tools menu). 5. Browse to the tb_filter_design.tcl script and click Open. 6.
Stratix II Professional Filtering Lab To display as an analog waveform, right-click on the signal and select Format > Analog. This opens the Wave Analog window. Turn on Analog Step and click OK. Figure 21.
Stratix II Professional Filtering Lab Exercise 4: Analyze & Compare the Results in Hardware In Exercise 4, you will do the following tasks: 1. “Set Up the Stratix II EP2S180 DSP Development Board for Hardware Analysis”. 2. “Review Changes Made to the Filtering Lab Design” on page 35. 3. “Configure the EP2S180 FPGA With the Filtering Lab Design” on page 37. 4. “Perform SignalTap II Analysis” on page 37.
Stratix II Professional Filtering Lab Figure 22. Simulink Design for Exercise 4 Set Up the Stratix II EP2S180 DSP Development Board for Hardware Analysis Before performing hardware analysis, you must connect two cables to the Stratix II EP2S180 DSP development board, the SMA cable and the USB-Blaster™ cable. The DSP Development Kit, Stratix II Professional Edition includes both cables.
Exercise 4: Analyze & Compare the Results in Hardware To connect the cables, follow these steps (see Figure 23): 1. Connect the SLP-50 anti-aliasing filter to one end of the SMA cable. a. Connect the anti-aliasing filter to the D/A converter labeled DAC CHANNEL A (J31). b. Connect the other end of the SMA cable to the A/D converter labeled ADC CHANNEL A (J32). Figure 23.
Stratix II Professional Filtering Lab 2. Connect the USB-Blaster cable to your PC and to the Stratix II EP2S180 DSP development board’s 10-pin JTAG (J21) connector to directly configure the EP2S180 FPGA, as shown in Figure 24. 1 Insert the USB-Blaster cable into J21, so that the cable end labeled TARGET SIDE faces upward as shown in “JTAG Connector (J21) and USB-Blaster Cable” on page 32. Figure 24.
Exercise 4: Analyze & Compare the Results in Hardware 3. Add jumpers to J3 and J19 (see Figure 25): a. Place a jumper on pins 1 and 2 on J3 to connect the on-board 100 MHz oscillator to ADC CHANNEL A. b. Place a jumper on pins 1 and 2 on J19 to connect the on-board 100 MHz oscillator to DAC CHANNEL B. Figure 25.
Stratix II Professional Filtering Lab 4. Connect the power cable to the board and plug the other end into a power outlet. Figure 26. Connected Power Cable 5. 34 To power-up the board, place SW1 (POWER switch) in the ON position. f For detailed instructions on connecting the cables and powering up the Stratix II EP2S180 DSP development board, see the Stratix II EP2S180 DSP Development Board Reference Manual.
Exercise 4: Analyze & Compare the Results in Hardware Review Changes Made to the Filtering Lab Design To review the changes made to the filtering lab design, follow these steps: 1. Run the MATLAB software. 2. In the Current Directory list in the desktop toolbar, browse to the directory: \StratixII_Pro_DSP_Kit-v1.0.0 \Examples\HW\ Lab\Filtering\Exercise4 3. Click OK. 4. Choose Open (File menu), select filter_design.mdl, and click Open. 5. Review the schematic design (see Figure 22).
Stratix II Professional Filtering Lab 6. Double-click the Counter Circuit block to view the counter circuit subsystem, as shown in Figure 27. Figure 27. Counter Circuit Block When the clken input signal is high, the counter circuit generates a signal count_reached that generates a pulse every 4,095 clock cycles. In “Perform SignalTap II Analysis”, the falling edge of the signal count_reached is set as a trigger in the SignalTap II Analysis block.
Exercise 4: Analyze & Compare the Results in Hardware Configure the EP2S180 FPGA With the Filtering Lab Design To configure the EP2S180 FPGA, follow these steps: 1. Double-click the SignalCompiler block (see Figure 22). 2. In the SignalCompiler 5.0.1 - page 1 of 2 dialog box, turn on Re-run update diagram to solve workspace parameters. 3. Click Analyze. 4. In the SignalCompiler 5.0.1 - page 2 of 2 dialog box, under Hardware Compilation, under Single step compilation, click 1 - Convert MDL to VHDL.
Stratix II Professional Filtering Lab 5. Right-click on adder_result_tap and select Unsigned Decimal as the radix, as shown in Figure 28. Figure 28. Specify the Radix as Unsigned Decimal for adder_result_tap 38 6. In the Select your JTAG cable list, select USB-Blaster. 7. To run the analyzer, click Start Analysis. DSP Builder runs a Tcl script to instruct the SignalTap II logic analyzer to begin analyzing the data and wait for the trigger conditions to occur. 8.
Exercise 4: Analyze & Compare the Results in Hardware Figure 29 shows the locations of SW4 and SW5 on the Stratix II EP2S180 DSP development board. Figure 29. SW4 & SW5 on the Stratix II Professional EP2S180 DSP Development Board SW4 SW5 10. To display the results in a MATLAB plot, click OK in the SignalTap II Analysis dialog box (see Figure 28 on page 38), after the SignalTap II logic analyzer finishes acquiring data and displays the message “SignalTap II Analysis is complete.
Stratix II Professional Filtering Lab 11. Close the MATLAB plot of the data displayed in binary format. Examine the MATLAB plot of the data displayed in the radix you specified. Zoom in on the fir_result_tap signal, as shown in Figure 30. The fir_result_tap signal is a scaled version of the 1-MHz sinusoid. Figure 30. SignalTap II Signals in the Time Domain 12. Return to the MATLAB Workspace browser. 13.
Exercise 4: Analyze & Compare the Results in Hardware 14. To view the fast Fourier transform (FFT) of the unfiltered data, type the following command in the MATLAB Command Window: plot_fft(adder_result_tap,'Frequency Response - Unfiltered Data',10e7) r Parameters in this command line include the following: ● ● ● adder_result_tap is the name of the signal represented by the adder_result_tap SignalTap II block in the Simulink model. Frequency Response - Unfiltered Data is the title of the plot.
Stratix II Professional Filtering Lab ● ● Filtered Response – Filtered Data is the title of the plot. 10e7 is the sampling frequency (100 MHz). A MATLAB plot displays the frequency response of the filtered data, as shown in Figure 32. Figure 32. FFT Response of fir_result_tap—Filtered Data 16. Compare the plots generated in step 14 on page 41 and step 15 on page 41 with the plot generated in step 7 of “Exercise 2: Simulate the Model in Simulink” on page 21.
Troubleshooting Troubleshooting This section contains the following troubleshooting questions and solutions. Why do I get errors when I load the Simulink design filter_design.mdl? In order to load the filter_design.mdl successfully, you must have the correct versions of the DSP Builder, MATLAB/Simulink, and IP cores. Refer to the section “Before You Begin” on page 3 for details.
