User guide

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Troubleshooting
Troubleshooting
This section contains the following troubleshooting questions and
solutions.
Why do I get errors when I load the Simulink design
filter_design.mdl?
In order to load the filter_design.mdl successfully, you must have the
correct versions of the DSP Builder, MATLAB/Simulink, and IP cores.
Refer to the section “Before You Begin” on page 3 for details.
Why is my SignalTap II filtered signal different from the one
Figure 30 shows?
If the SMA cable is not securely connected between DAC CHANNEL A
and ADC CHANNEL A, you will not see a signal at the output of the FIR
filter during SignalTap II analysis. Ensure the correct settings for the
jumpers J30, J35 and J37, as specified in “Set Up the Stratix II EP2S180 DSP
Development Board for Hardware Analysis” on page 30. Figure 25 on
page 33 shows the jumper settings.
Conclusion
The Stratix II Professional filtering lab design provides a basic design
example using the on-board A/D converter and the on-board D/A
converter. It demonstrates SignalTap II analysis as a real-time FPGA
signal acquisition feature in the DSP Builder environment of Simulink.